start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

	.align	2
	
/**/

/*
 *  Simple serial output routine used to communicate messages
 *  during prom setup before 'real' driver is running.
 *  This code simply displays a string of chars on the console.
 */

serial_out:
	lis	30, HIADJ(COM1_BASE_ADDR)
	addi	30, 30, LO(COM1_BASE_ADDR)
	li	31, 1
	stb	31, 4(30)	/* DTR on */
	IORDER
	li	31, 0x80	/* Get to divisor latch */
	stb	31, 3(30)
	IORDER
	li	31, 0x0C	/* Baud rate */
	stb	31, 0(30)
	IORDER
	li	31, 0x0
	stb	31, 1(30)
	IORDER
	li	31, 0x3		/* 8 bits no parity */
	stb	31, 3(30)
	IORDER

	lis	31, 0x0002	/* let sio stabilize */
	mtctr	31
1:
	bdnz	1b

2:
	lbz	31, 0(4)
	cmpwi	31, 0x0
	beq	4f
3:
	lbz	31, 5(30)
	andi.	31, 31, 0x20
	beq	3b		/* Wait for tx buffer empty */

	lbz	31, 0(4)
	stb	31, 0(30)	/* send char */
	IORDER
	addi	4, 4, 1
	b	2b

4:
	blr			/* return */
/**/

	.globl	put_hex_word
put_hex_word:
	or	4, 3, 3
	mflr	5
	srwi	3, 4, 28
	bl	put_hex
	srwi	3, 4, 24
	bl	put_hex
	srwi	3, 4, 20
	bl	put_hex
	srwi	3, 4, 16
	bl	put_hex
	srwi	3, 4, 12
	bl	put_hex
	srwi	3, 4, 8
	bl	put_hex
	srwi	3, 4, 4
	bl	put_hex
	or	3, 4, 4
	bl	put_hex
	li	3, 32
	bl	tgt_putchar
	mtlr	5
	blr
	
put_hex:
	andi.	3, 3, 0xf
	lis	9, HIADJ(hexchars)
	addi	9, 9, LO(hexchars)
	add	9, 9, 3
	add	9, 9, 16
	lbz	3, 0(9)
	b	tgt_putchar

	.rodata
hexchars:
	.ascii	"0123456789abcdef"

	.section ".text"
	.align	2

	.globl	tgt_putchar
tgt_putchar:
	lis	9, HIADJ(COM1_BASE_ADDR)
	addi	9, 9, LO(COM1_BASE_ADDR)
1:
	lbz	0, 5(9)
	andi.	0, 0, 0x20
	beq	1b

	stb	3, 0(9)
	blr

init_sdram_bank0:

//################################################################
// enable drambank0 at address 0x00000000...0x0x3FFFFFF (64MByte)
// it is assumed that there is a 64/128/256MByte
// bank at bank0 available at powercore all the time!
// remember:
// r4 = PCI configuration address 
// r5 = PCI configuration data    
// r6 = mpc106 pci cfg addr : 0xXX000080; little endian!!!
// r8 = scratch value
// r9 = scratch
// 10= scratch
// It is assumed that MPC107 is accessible via config cycles on
// the local PCIbus at PCIbus 0 via value 0x80000000 (no probing!).
//################################################################

//preset config. addr/data addresses
	addis	4,0,0xFEC0
	ori	4,4,0x0000
	addis	5,0,0xFEE0
	ori	5,5,0x0000

//###############################################################
// setup RAM_TYPE=0 SDRAM mode (MCCR1,0xF0,bit17)  
// (Must be manipulated before BUF_TYPE[0]=1 is manipulated)        
//##############################################################
//preset pci slot 0 for mpc107 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

//RAM_TYPE, value=0, offset 0xF0, enable/enable mode
	addis   0,0,0xF000
	or	0,6,0

//do configuration read to offset F0h to preserve bits 31..18,16..0 little endian!!!
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f8]0, 15[f9]8, 23[fa]16, 31[fb]24), little endian value!!!
//clear bit 17, RAM_TYPE=0
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0xFFFF
	andi.	8,8,0xFDFF    //clear bit 17 little endian!!!
	or	8,9,8

//do configuration write to offset F0h, little endian value!!!
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio


//#################################################################
// setup INLINE_WR_EN=0, In-line parity disabled (MCCR2,0xF4,bit19)
// (Must be 1 for In-line ECC/Parity)
//################################################################
//preset pci slot 0 for mpc107 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

//INLINE_WR_EN, clear bit 19 = 0, offset 0xF4,
	addis   0,0,0xF400
	or	0,6,0

//do configuration read to offset F4h to preserve bits 31..20,18..0;
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f0]0, 15[f1]8, 23[f2]16, 31[f3]24), little endian value!!!
//clear bit 19, disable In-line ECC/Parity
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0xFFFF
	andi.	8,8,0xF7FF    //clear bit 19 little endian!!!
	or	8,9,8

//  	ori	8,8,0x0800    // Parity/ECC: must be 1


//do configuration write to offset F4h;
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio

//#################################################################
//setup INLINE_RD_EN=0, In-line parity disabled (MCCR2,0xF4,bit18)
//(Must be 1 for In-line ECC/Parity)
//##################################################################
//preset pci slot 0 for mpc107 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

//INLINE_RD_EN, clear bit 18 = 0, offset 0xF4,
	addis   0,0,0xF400
	or	0,6,0

//do configuration read to offset F4h to preserve bits 31..19,17..0;
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f0]0, 15[f1]8, 23[f2]16, 31[f3]24), little endian value!!!
//clear bit 18, disable In-line ECC/Parity
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0xFFFF
	andi.	8,8,0xFBFF    //clear bit 18 little endian!!!
	or	8,9,8

//  	ori	8,8,0x0400    // Parity/ECC: must be 1


//do configuration write to offset F4h;
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio

//#################################################################
//# setup RMW_PAR=0, RMW parity disabled (MCCR2,0xF4,bit0)
//# (Must be 1 for In-line ECC/Parity)
//##################################################################
//preset pci slot 0 for mpc107 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

//RMW_PAR, clear bit 0 = 0, offset 0xF4,
	addis   0,0,0xF400
	or	0,6,0

//do configuration read to offset F4h to preserve bits 31..1;
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f0]0, 15[f1]8, 23[f2]16, 31[f3]24), little endian value!!!
//clear bit 0, disable RMW parity
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0xFEFF    //clear bit 0 little endian!!!
	andi.	8,8,0xFFFF    
	or	8,9,8

//  	oris	8,8,0x0100    // Parity/ECC: must be 1


//do configuration write to offset F4h;
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio
	
// ----------added by voho------------------------------------------------
	
//###############################################################
//# setup registered data buffers BUF_TYPE[1]=1 (MCCR4,0xFC,bit20)
//# for normal mode 
//################################################################ 
//preset pci slot 0 for mpc107 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

//BUF_TYPE[1], set bit 20 = 1, offset 0xFC,
	addis   0,0,0xFC00
	or	0,6,0

//do configuration read to offset FCh to preserve bits 31..21,19..0;
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio
	
// ------------------modified by voho----------------------------------
//8 = (7[f0]0, 15[f1]8, 23[f2]16, 31[f3]24), little endian value!!!
// set bit 20, enable inline ECC
  	ori	8,8,0x1000
	
//8 = (7[f0]0, 15[f1]8, 23[f2]16, 31[f3]24), little endian value!!!
//clear bit 20, BUF_TYPE[1]=0
// 	or	9,8,8	//move (8)->(9)
// 	andis.	9,9,0xFFFF    // (9) = 0xXXXX0000
//	andi.	8,8,0xEFFF    // mask bit20 to zero
//				// (8) = 0x0000AXXX
// 	or	8,9,8        // (8) = 0xXXXXAXXX
// ------------------------------------------------------------------
//do configuration write to offset FCh;
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio
	

//###############################################################
//# setup registered data buffers BUF_TYPE[0]=0 (MCCR4,0xFC,bit22)
//# (Do not use In-line without ECC/Parity)
//################################################################ 
//preset pci slot 0 for mpc107 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000	
	ori	6,6,0x0080

//BUF_TYPE[0], set bit 22 = 0, offset 0xFC,
	addis   0,0,0xFC00
	or	0,6,0

// do configuration read to offset FCh to preserve bits 31..23,21..0;
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

// ------------------modified by voho----------------------------------

//8 = (7[f0]0, 15[f1]8, 23[f2]16, 31[f3]24), little endian value!!!
//clear bit 22, BUF_TYPE[1]=0
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0xFFFF    // (9) = 0xXXXX0000
	andi.	8,8,0xBFFF    // mask bit22 to zero
				// (8) = 0x0000AXXX
	or	8,9,8        // (8) = 0xXXXXAXXX

//set bit 22, enable inline ECC
//  	ori	8,8,0x4000

// ------------------------------------------------------------------

//do configuration write to offset FCh;
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio

//######################################################################################
//# MCCR 1, 0xF0, PCKEN            , bit16 = 0 per default, disable parity
//# MCCR 2, 0xF4, EDO              , bit16 = 0 per default, no EDO mode
//# MCCR 2, 0cF4, ECC_EN           , bit17 = 0 per default, no ECC - must be 0 for SDRAM
//# MCCR 2, 0xF4, INLINE_ECC_OR_PAR, bit20 = 0 per default, ECC on SDRAM Data bus
//#
//# "MEM_PERR_EN" and "MB_ECC_ERR_EN" are handled at file "asm_routines.s"
//######################################################################################

//#############################################
//# setup memory bank0 start address 0x00000000
//#############################################
//preset pci slot 0 for mpc106 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

//mem_start03, offset 80, 7..0  = 00XXYYZZ, 0 =0x80XX0080;
	addis   0,0,0x8000
	or	0,6,0

//do configuration read to offset 80h to preserve bits 31..8;
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f0]0, 15[f1]8, 23[f2]16, 31[f3]24), little endian value!!!
//clear bits 7..0, bank 0 start
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0x00FF    // (9) = 0x00CD0000
	andi.	8,8,0xFFFF    // (8) = 0x0000EFGH
	or	8,9,8        // (8) = 0x00CDEFGH

//do configuration write to offset 80h to clear bits 7..0
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio

//preset pci slot 0 for mpc106 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

//mem_start_ext03, offset 88, 1..0  = W0XXYYZZ, 0 =0x88XX0080
	addis   0,0,0x8800
	or	0,6,0

//do configuration read to offset 88h to preserve bits 31..2, little endian!!!
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f0]0, 15[f1]8, 23[f2]16, 31[f3]24), little endian value!!!
//clear bits 1..0, bank 0 ext. start
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0xFCFF    /* (9) = 0xAB'CD0000 */
	andi.	8,8,0xFFFF    /* (8) = 0x0000EFGH */
	or	8,9,8        /* (8) = 0xAB'CDEFGH */

//do configuration write to offset 88h, little endian!!!
        eieio
	stw	0,0(4)
	eieio
	stw	8,0(5)
	eieio

// start address for bank0 = 0x00000000

//######################################################
// setup memory bank0 end address 0x03FFFFFF ( 64 MByte)
// modify here for other sizes:   0x07FFFFFF (128 MByte)
//                                0x0FFFFFFF (256 MByte)
// onboard SDRAM size can be 64/128/256 MByte
// DCCR A at offset 0xFE000308, ONBOARD_MEM, bit 3..0
// 0001b =  64MB, 0x03FFFFFF, SDRAM
// 0010b = 128MB, 0x07FFFFFF, SDRAM
// 0011b = 256MB, 0x0FFFFFFF, SDRAM
// (others are not yet defined, Jul/28/1999)
//######################################################
//preset pci slot 0 for mpc106 = 0x80000000; little endian; long swapped;
	addis	6,0,0x0000
	ori	6,6,0x0080

// mem_end03, offset 90, 7..0  = 00XXYYZZ, 0 =0x90XX0080;
	addis   0,0,0x9000
	or	0,6,0

//do configuration read to offset 90h, little endian!!!
        eieio
	stw	0,0(4)
	eieio
	lwz	8,0(5)
	eieio

//8 = (7[f0]0, 15[f1]8, 23[f2]16, 31[f3]24), little endian value!!!

//clear bits 7..0, bank 0 end
	or	9,8,8	//move (8)->(9)
	andis.	9,9,0x00FF    // (9) = 0x00CD0000
	andi.	8,8,0xFFFF    // (8) = 0x0000EFGH
	or	8,9,8        // (8) = 0x00CDEFGH

// or value 0x3F to build end address 0x3F for 64MB per default
	oris	8,8,0x3F00	// (8) = 0x3FCDEFGH