start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$Id: start.S,v 1.4 2002/11/15 22:39:58 patrik Exp $ */

/*
 * Copyright (c) 2000 Opsycon AB  (www.opsycon.se)
 * Copyright (c) 2001 ipUnplugged AB (www.ipunplugged.com)
 * Copyright (c) 2002 Patrik Lindergren (www.lindergren.com)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Patrik Lindergren.
 *	This product includes software developed by ipUnplugged AB.
 *	This product includes software developed by Opsycon AB.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */


#include "target/pmon_target.h"

#include <include/cpci680.h>
#include <powerpc.h>
#include <pmon/dev/mpc107reg.h>

	.space	0x100

	.globl	_start
	.globl	start
_start:
start:

	.globl	pmon_stack
stack = start - 0x4000		/* 16K PMON stack */
pmon_stack = start		/* Top of stack */
	.globl	pmon_intstack
intstack = stack - 0x2000	/* 8k PMON interrupt stack */
pmon_intstack = stack		/* Top of stack */

	/* Clear MSR to diable interrupts and checks */
	andi.	1, 1, 0x0
	sync
	mtmsr	1		/* Clear MSR */
	isync

	/* Zero-out registers  */
	andi.   0, 0, 0
	mtspr   SPRG0, 0
	mtspr   SPRG1, 0
	mtspr   SPRG2, 0
	mtspr   SPRG3, 0

	/* Set HID0 to known state */
	lis	3, HI(HID0_NHR)
	ori	3, 3, LO(HID0_NHR)
	mfspr	4, HID0
	and	3, 4, 3		/* Clear other bits */
	mtspr	HID0, 3
	sync
	
	/* Set MPU/MSR to a known state. Turn on FP */
 	lis	3, HI(PPC_MSR_FP)
	ori	3, 3, LO(PPC_MSR_FP)
	sync
	mtmsr 	3
	isync

	/* Init the floating point control/status register */
 	mtfsfi  7,0x0
	mtfsfi  6,0x0
	mtfsfi  5,0x0
	mtfsfi  4,0x0
	mtfsfi  3,0x0
	mtfsfi  2,0x0
	mtfsfi  1,0x0
	mtfsfi  0,0x0
	isync

	/* Initialize floating point data regs to known state */

	bl	ifpdr_value
	.long	0x3f800000	# 1.0  

ifpdr_value:
	mfspr	3,8
	lfs	0,0(3)
	lfs	1,0(3)
	lfs	2,0(3)
	lfs	3,0(3)
	lfs	4,0(3)
	lfs	5,0(3)
	lfs	6,0(3)
	lfs	7,0(3)
	lfs	8,0(3)
	lfs	9,0(3)
	lfs	10,0(3)
	lfs	11,0(3)	
	lfs	12,0(3)
	lfs	13,0(3)
	lfs	14,0(3)
	lfs	15,0(3)
	lfs	16,0(3)
	lfs	17,0(3)
	lfs	18,0(3)
	lfs	19,0(3)
	lfs	20,0(3)
	lfs	21,0(3)	
	lfs	22,0(3)
	lfs	23,0(3)
	lfs	24,0(3)
	lfs	25,0(3)
	lfs	26,0(3)
	lfs	27,0(3)
	lfs	28,0(3)
	lfs	29,0(3)
	lfs	30,0(3)
	lfs	31,0(3)
	sync

	/* Clear BAT and Segment mapping registers */
	andi.	1, 1, 0x0
	mtibatu	0, 1
	mtibatu	1, 1
	mtibatu	2, 1
	mtibatu	3, 1
	mtdbatu	0, 1
	mtdbatu	1, 1
	mtdbatu	2, 1
	mtdbatu	3, 1
	isync
	sync
	sync
	lis	1, 0x8000
	isync
	mtsr	0, 1
	mtsr	1, 1
	mtsr	2, 1
	mtsr	3, 1
	mtsr	4, 1
	mtsr	5, 1
	mtsr	6, 1
	mtsr	7, 1
	mtsr	8, 1
	mtsr	9, 1
	mtsr	10, 1
	mtsr	11, 1
	mtsr	12, 1
	mtsr	13, 1
	mtsr	14, 1
	mtsr	15, 1
	isync
	sync
	sync

	/* Turn off caches and invalidate them */
	mfspr	3, L2CR
	rlwinm  3, 3, 0, 1, 31     /* turn off the L2 enable bit */
	mtspr	L2CR, 3
	isync

	oris	3, 3, HI(L2CR_L2I)
	mtspr	L2CR, 3
	sync
1:
	mfspr	3, L2CR
	andi.	3, 3, LO(L2CR_L2IP)
	cmpwi	3, LO(L2CR_L2IP)
	beq	1b		/* Wait for invalidate done */

	/* Invalidate L1 Cache */
	mfspr   3, HID0
	isync
	rlwinm  4, 3, 0, 18, 15	/* Clear d16 and d17 to disable L1 cache */
	sync
	isync
	mtspr   HID0, 4 	/* turn off caches */
	isync

	lis	3, 0
	ori	3, 3, LO(HID0_ICFI)	/* Invalidates instruction caches */
	or	4, 4, 3
	sync
	isync
	mtspr	HID0, 4
	andc	4, 4, 3
	isync

	lis	3, 0
	ori	3, 3, LO(HID0_DCFI)	/* Invalidates data caches */
	or	4, 4, 3
	sync
	isync
	mtspr	HID0, 4
	andc	4, 4, 3
	isync

	li	11, 0x2000	/* No harm */
	mtspr	CTR, 11
1:
	bdnz	1b

	isync
	mfspr	4, HID0
	isync
	ori	4, 4, (HID0_ICE | HID0_ICFI)
	isync
	mtspr	HID0, 4			/* turn on i-cache for speed */
	rlwinm	4, 4, 0, 21, 19		/* clear the ICFI bit */
	isync
	mtspr	HID0, 4

	/* Get CPU type */
	mfspr	28, PVR
	rlwinm	28, 28, 16, 16, 31

	/* Set r16 to the load vs link offset. */
	bl	1f
1:
	mflr	3
	lis	16, 0xffff
	and.	16, 16, 3
	lis	4, HI(start)
	sub	16, 16, 4		/* R16 is now load offset */

	/*
	 *  Find out if executing in ROM or RAM. Note memory size wired to 256 Mb.
	 */
	lis	15, 0x0400		/* Memory size accumulator = 64 MB */
	lis	4, 0xf000		/* Last segment */
	and.	4, 4, 3
	beq	in_ram			/* We are ram loaded! */

/*
 * This is a cold boot startup. Do HW initialisation
 */
	/* Fixed regs 20 = PCI CONFIG ADDR, 21 = PCI_CONFIG_DATA, 22 = CONF DEV */
	lis	20, HI(MPC107_CONF_ADDR)
	lis	21, HI(MPC107_CONF_DATA)
	lis	22, 0x8000		/* config space access enable */

	/* Set EUMBBAR to default value */	
	MPC_CFG_WR(MPC107_CFG_EUMBBAR, MPC107_EUMBAR)
	MPC_CFG_WR(MPC107_CFG_PCSRBAR, MPC107_EUMBAR)

#if 0
	/* Set up Processor Interface Configuration Register 1 */
	MPC_CFG_RD(MPC107_CFG_PICR1)
	lis	0, 0xff38
	ori	0, 0, 0x0300
	and	4, 4, 0
	lis	0, 0x0006		/* CPU type = 603/7xx/74xx and MAP B */
	ori	0, 0, 0x1890
	or	4, 4, 0
	MPC_CFG_RWR(MPC107_CFG_PICR1)
	sync
#endif
	/* Set up the Address Map B Option register */
	MPC_CFG_AD(MPC107_CFG_AMBOR)
	lbz	4, 0(21)
	andi.	4, 4, 0x00
	stb	4, 0(21)
	IORDER
#if 0
	/* Set PCI command to default values and clear any error status. */
	MPC_CFG_RD(MPC107_PCI_CMD)
	lis	0, 0xffff
	ori	0, 0, 0xfca0
	and	4, 4, 0			/* Preserve bits */
	ori	4, 4, 0x0106		/* SERR, MASTER, MEMORY ENABLE */
	MPC_CFG_RWR(MPC107_PCI_CMD)
#endif
	
	/* Disable error reporting */
	MPC_CFG_AD(MPC107_CFG_ERR_EN1)
	lbz	4, 0(21)
	andi.	4, 4, 0xfb
	stb	4, 0(21)
	IORDER

	/* Disable error reporting */
	MPC_CFG_AD(MPC107_CFG_ERR_EN2)
	lbz	4, 0(21)
	andi.	4, 4, 0xf7
	stb	4, 0(21)
	IORDER

// modify Boot FLASH memory configuration registers to optimized speed
	b		boot_flash_speed
_boot_flash_is_on_speed: 

# initialize the MPC106 processor configuration registers (PICR)
        b		picr_init
_picr_is_init:		

	b               mpc10X_error_clear
mpc10X_err_is_clr:

	b init_sdram_bank0
memory_runs:

/*
 *  Here we need to enable the IBAT/DBAT (after setup) to be able to
 *  access 0xfff00000+ if processor is 740/750/7400!
 */
        IBAT_SETUP(0, 0x00001fff, 0x0000001a)	/* Ram segment */
        IBAT_SETUP(1, 0xf0001fff, 0xf000002a)	/* Boot rom segment */
        IBAT_SETUP(2, 0x00000000, 0x00000000)	/* Disable */
        IBAT_SETUP(3, 0x00000000, 0x00000000)	/* Disable */
        DBAT_SETUP(0, 0x00001fff, 0x0000001a)	/* Ram segment */
        DBAT_SETUP(1, 0x80001fff, 0x8000002a)	/* PCI mem */
        DBAT_SETUP(2, 0x70001fff, 0x7000002a)	/* Extended ROM/Flash */
        DBAT_SETUP(3, 0xf0001fff, 0xf000002a)	/* PCI I/O, Boot rom segment */

	mfmsr	4
	ori	4, 4, 0x0010	/* Translation enable */
	isync
	mtmsr	4
	sync

	/* Enable L1 data cache */
	mfspr	4, HID0	
	ori	4, 4, LO(HID0_ICE | HID0_DCE | HID0_SGE | HID0_BTIC | HID0_BHTE)	/* Enable D-cache */
	isync
	mtspr	HID0, 4	
	isync
/*
 *  Set up on chip L2 cache controller.
 */
	lis	4, HI(L2CR_L2SIZ_1024 | L2CR_L2CLK_3 | L2CR_L2RAM_PIPE)
	ori	4, 4, 0x0000
	
	mtspr	L2CR, 4
	sync
	mfspr	5, L2CR
	oris	5, 5, HI(L2CR_L2I)
	mtspr	L2CR, 5
	sync
	
2:
	mfspr	3, L2CR
	andi.	3, 3, LO(L2CR_L2IP)
	cmpwi	3, LO(L2CR_L2IP)
	beq	2b		/* Wait for invalidate done */

	oris	4, 4, HI(L2CR_L2E)
	mtspr	L2CR, 4			/* Enable L2 cache */
	sync
	isync

/* Output 'alive' message on console */
	lis	4, HIADJ(main_msg)
	addi	4, 4, LO(main_msg)
	add	4, 4, 16
	bl	serial_out

/*
 *  We scrub the entire memory to get rid of potential parity errors.
 */
#if 0	
	lis	15, 0x10		/* Clear first 1MB */
	srwi	3, 15, 2		/* Mem size div 4 */
	li	4, 0x4000		/* Start from 0x4000 to preserve */
	sub	3, 3, 4		/* message areas */
	mtctr	3
1:
	stw	4, 0(4)		/* Zero out what will be the stack */
	addic	4, 4, 0x4
	bdnz	1b
#endif
	b	in_rom
/*
 *  RAM memory should now be operational, we can call C-code (some
 *  restrictions still do apply, like usage of initialised vars).
 */
	.globl in_ram
in_ram:
	lis	4, HIADJ(ram_msg)
	addi	4, 4, LO(ram_msg)
	add	4, 4, 16
	bl	serial_out

	.globl in_rom
in_rom:	
	lis	4, HI(start)
	addi	1, 4, -64		/* RAM START++ will be overwritten */
	stw	15, 8(1)		/* Save away memory size */

	add	3, 4, 16
	bl	copytoram		/* Go do PPC initialization */

	cmpwi	3, 0x0
	beq	__go			/* Verify after copy succeded */

	or	18, 3, 3
	bl	put_hex_word
	lwz	3, 0(18)
	bl	put_hex_word
	sub	18, 18, 16
	lwz	3, 0(18)
	bl	put_hex_word

	lis	4, HIADJ(fail_msg)
	addi	4, 4, LO(fail_msg)
	b	bootinit_fail
/*
 *  All stations are GO for takeoff.
 *  Lets go to the other end of the universe!
 */
__go:
	lwz	3, 8(1)			/* Memorysize */

	lis	1, HIADJ(STACKBASE)
	addi	1, 1, LO(STACKBASE)
	mtsprg	0, 1
	addi	1, 1, LO(STACKSIZE-64)
	li	0, 0x0		/* Mark end of frames on stack */
	stw	0, 0(1)
	stw	0, 4(1)

	lis	4, HIADJ(initppc)
	addi	4, 4, LO(initppc)
	mtlr	4
	blr


	.rodata
main_msg:
	.asciz	"\r\n\r\nPMON2000 PowerPC Initializing. Standby...\r\n"
ram_msg:
	.asciz	"\r\n\r\nPMON2000 PowerPC Ramloaded. Standby...\r\n"
fail_msg:
	.asciz	" <= PANIC! Verify after copy to ram failed!\r\n"

	.section ".text"
	.align	2
/**/
bootinit_fail:
	add	4, 4, 16
	bl	serial_out
1:
	b	1b

	.section ".text"