start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

	GT_REGWR(SCS_1_HIGH_DECODE_ADDRESS, 0x000)	/* disable */
	b	sdram_slot1_config

sdram_slot0_2bank:
	DBGPRINTSTR("Dual bank\r\n")
	GT_REGWR(SCS_0_LOW_DECODE_ADDRESS, 0)	/* Module starts at address 0 */
	GT_REGAD(SCS_1_LOW_DECODE_ADDRESS)
	srwi	r6, r17, 20
	stwbrx	r6, 0, (r5) 
	GT_REGAD(SCS_0_HIGH_DECODE_ADDRESS)
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 
	GT_REGAD(SCS_1_HIGH_DECODE_ADDRESS)
	srwi	r6, r17, 20
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 

/*  Configure SECONDARY SDRAM module if poulated */

sdram_slot1_config:

#ifdef notyet
	cmpwi	r18, 0
	beq	sdram_set_param		/* empty */

	DBGPRINTSTR("INIT SECONDARY SDRAM module\r\n")
	li	r3, 0x41f		/* Get bank density */
	bl	boot_i2c_read
	or	r12, r3, r3
	li	r3, 0x404		/* Get bank density */
	bl	boot_i2c_read
	or	r13, r3, r3
	li	r3, 0x415		/* Get module type */
	bl	boot_i2c_read
	or	r11, r3, r3

	li	r3, 0x405		/* Get number of module banks */
	bl	boot_i2c_read
	cmpwi	r3, 2
	beq	sdram_slot1_2bank

	DBGPRINTSTR("Single bank\r\n")
	GT_REGAD(SCS2_LOW)		/* Module starts at address 0 */
	srwi	r6, r17, 21		/* Make end value for GT reg */
	stwbrx	r6, 0, (r5) 
	GT_REGAD(SCS2_HIGH)
	add	r6, r17, r18
	srwi	r6, r6, 21		/* Make end value for GT reg */
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 
	b	sdram_set_param

sdram_slot1_2bank:
	DBGPRINTSTR("Dual bank\r\n")
	GT_REGAD(SCS2_LOW)		/* Module starts at address 0 */
	srwi	r6, r17, 21		/* Make end value for GT reg */
	stwbrx	r6, 0, (r5) 
	GT_REGAD(SCS3_LOW)
	srwi	r6, r17, 21
	srwi	r4, r18, 21
	add	r6, r6, r4
	stwbrx	r6, 0, (r5) 
	GT_REGAD(SCS2_HIGH)
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 
	GT_REGAD(SCS3_HIGH)
	add	r6, r17, r18
	srwi	r6, r6, 21		/* Make end value for GT reg */
	addi	r6, r6, -1
	stwbrx	r6, 0, (r5) 
#endif

sdram_set_param:

/* Init parameters. Both modules assumed to be the same. */

	DBGPRINTSTR("Setting SDRAM parameters\r\n")
	lis	r6, 0
	ori	r6, r6, 0x8000
	cmpwi	r12, 0x10			/* 64 MB */
	beq	sdram_set_density
	cmpwi	r12, 0x20			/* 128 MB */
	beq	sdram_set_density

	ori	r6, r6, 0xc000
	cmpwi	r12, 0x40			/* 256 MB */
	beq	sdram_set_density
	cmpwi	r12, 0x80			/* 512 MB */
	beq	sdram_set_density

	li	r6, 0x4000			/* 16 MB */
	cmpwi	r13, 10
	beq	sdram_set_density
	li	r6, 0x00000861			/* Four chip module ? */

sdram_set_density:
        GT_REGAD(SDRAM_BANK0PARAMETERS)
	stwbrx	r6, 0, (r5)
        GT_REGAD(SDRAM_BANK1PARAMETERS)
	stwbrx	r6, 0, (r5)
        GT_REGAD(SDRAM_BANK2PARAMETERS)
	stwbrx	r6, 0, (r5)
        GT_REGAD(SDRAM_BANK3PARAMETERS)
	stwbrx	r6, 0, (r5)

/*  Check if module is registred or not and set up accordingly */

	cmpwi	r11, 0				/* Unbuffered? */
	beq	sdram_set_unbuffered

	DBGPRINTSTR("SDRAM Registred\r\n")
        GT_REGWR(SDRAM_CONFIGURATION, 0x00800200) /* Set registered */
	b	sdram_set_mode

sdram_set_unbuffered:
	DBGPRINTSTR("SDRAM Unbuffered\r\n")
        GT_REGWR(SDRAM_CONFIGURATION, 0x00000200) /* Set unbuffered */

sdram_set_mode:
	DBGPRINTSTR("SDRAM starting up!\r\n")
        GT_REGWR(SDRAM_ADDRESS_DECODE, 2)	/* Address decode */
        GT_REGWR(SDRAM_OPERATION_MODE, 3)	/* Register command */
	stw	r0, 0(r0)			/* Dummy write */
        GT_REGWR(SDRAM_OPERATION_MODE, 0)	/* Operation Mode normal */
/**/
	li	r3, 4
	bl	dbglednum

#if notyet
        GT_REGWR(GPP_LEVEL_CNTRL, 0x000002c6)	/* Serial Ports Mpx - RMII */
        GT_REGWR(SER_PORTS_MUX, 0x00000102)	/* Serial Ports Mpx - RMII */
        sync
#endif

/* Well, what the.... */
	mfmsr	3
	INT_MASK(3, 4)		/* Disable interrupt */
	ori	r3, r3, 0x3002	/* set FP, ME and RI */
	mtmsr	3

#if 0
/*
 *  Here we need to enable the IBAT/DBAT (after setup) to be able to
 *  access 0xfff00000+ if processor is 740/750!
 */
	IBAT_SETUP(0, 0x00001fff, 0x0000001a)	/* Ram segment */
	IBAT_SETUP(2, 0x00000000, 0x00000000)	/* Disable */
	IBAT_SETUP(3, 0x00000000, 0x00000000)	/* Disable */
	IBAT_SETUP(3, 0xf0001fff, 0xf000002a)	/* Boot rom segment */

	DBAT_SETUP(0, 0x00001fff, 0x0000001a)	/* Ram segment */
	DBAT_SETUP(1, 0x10001fff, 0x1000002a)	/* PCI mem */
	DBAT_SETUP(2, 0x80001fff, 0x0000002a)	/* PCI I/O */
	DBAT_SETUP(3, 0xf0001fff, 0xf000002a)	/* Boot rom segment */

/* Enable data address translation */
	mfmsr	r3
	ori	r3, r3, 0x0010
	isync
	mtmsr	r3
	sync
#endif

/* Invalidate all TLB entries */
	addis	r3, 0, 0
	ori	r3, r3, 0		# set up counter at 0x00000000 
	addis	r5, 0, 0x8		# high bound of 0x00080000 for 750/7400
tlblp:	
	tlbie	3
	sync
	addi	r3, r3, 0x1000
	cmp	r0, 0, r3, 5		# check if all 128 TLBs invalidated yet
	blt	tlblp

/*
 *  We scrub memory to get rid of potential parity errors.  Only
 *  clear the first 1MB of memory which is where PMON lives.
 */
#ifdef NOTYET
	DBGPRINTSTR("clearing memory\r\n")

	lis	r15, 0x10		/* Clear first 1MB */
	srwi	r3, r15, 2		/* Mem size div 4 */
	li	r4, 0x4000		/* Start from 0x4000 to preserve */
	sub	r3, r3, 4		/* message areas */
	mtctr	3
1:
	stw	r4, 0(r4)		/* Zero out what will be the stack */
	addic	r4, r4, 0x4
	bdnz	1b
#endif


in_ram:
	li	r3, 2
	bl	dbglednum

	DBGPRINTSTR("memory ok\r\n")

	li	r3, 5
	bl	dbglednum

	lis	r4, HI(start)
	addi	r1, r4, -64		/* RAM START++ will be overwritten */
	stw	r15, 8(r1)		/* Save away memory size */
	add	r3, r4, r16
	bl	copytoram		/* Go do PPC initialization */
	cmpwi	r3, 0
	beq	__go

/* Turn on bitfail LED to show that mem init failed */
	b	bootinit_fail

/*
 *  All stations are GO for takeoff.
 *  Lets go to the other end of the universe!
 */
__go:
	DBGPRINTSTR("copy to ram ok\r\n")

	li	r3, 0
	bl	dbglednum

	lwz	r3, 8(r1)			/* Memorysize */

	lis	1, HIADJ(STACKBASE)
	addi	1, 1, LO(STACKBASE)
	mtsprg	0, r1
	addi	r1, r1,STACKSIZE-64
	li	r0, 0x0		/* Mark end of frames on stack */
	stw	r0, 0(r1)
	stw	r0, 4(r1)

	lis	r4, HIADJ(initppc)
	addi	r4, r4, LO(initppc)
	mtlr	4
	blr

/**/
bootinit_nomem:
	PRINTSTR("PMON/2000 PPC ABORT! No RAM memory found!\r\n")
1:
	li	r3, 7
	bl	dbglednum	/* FLASH 111 <-> 001 - NO RAM */
	DELAY(10000000)
	li	r3, 1
	bl	dbglednum
	DELAY(10000000)
	b	1b

bootinit_fail:
	PRINTSTR("PANIC! Verify after copy to ram failed!\r\n")
1:
	li	r3, 7
	bl	dbglednum	/* FLASH 111 <-> 010 - RAM COPY ERR */
	DELAY(10000000)
	li	r3, 2
	DELAY(10000000)
	b	1b

/*
 *  Simple serial output routine used to communicate messages
 *  during prom setup before 'real' driver is running.
 *  This code simply displays a string of chars on the console.
 */

init_serial:
	lis	r30, HIADJ(COM1_BASE_ADDR)
	addi	r30, r30, LO(COM1_BASE_ADDR)
	li	r31, 1
	#stb	r31, 4(r30)	/* DTR on */
	stb	r31, 16(r30)	/* DTR on */
	IORDER
	li	r31, 0x80	/* Get to divisor latch */
	#stb	r31, 3(r30)
	stb	r31, 12(r30)
	IORDER
	li	r31, NS16550HZ/(16*CONS_BAUD)
	stb	r31, 0(r30)
	IORDER
	li	r31, 0x0
	#stb	r31, 1(r30)
	stb	r31, 4(r30)
	IORDER
	li	r31, 0x3		/* 8 bits no parity */
	#stb	r31, 3(r30)
	stb	r31, 12(r30)
	IORDER

	lis	r31, 0x0002	/* let sio stabilize */
	mtctr	31
1:
	bdnz	1b
	blr

	.globl	serial_out
serial_out:
	lis	r30, HIADJ(COM1_BASE_ADDR)
	addi	r30, r30, LO(COM1_BASE_ADDR)
1:
	lbz	r31, 0(r3)
	cmpwi	r31, 0
	beq	3f
2:
	lbz	r31, 20(r30)
	andi.	r31, r31, 0x20
	beq	2b		/* Wait for tx buffer empty */

	lbz	r31, 0(r3)
	stb	r31, 0(r30)	/* send char */
	IORDER
	addi	r3, r3, 1
	b	1b
3:
	blr			/* return */

	.globl	tgt_putchar
tgt_putchar:
	lis	r9, HIADJ(COM1_BASE_ADDR)
	addi	r9, r9, LO(COM1_BASE_ADDR)
1:
	lbz	r0, 20(r9)
	andi.	r0, 0, 0x20
	beq	1b
	stb	r3, 0(r9)
	IORDER
	blr

put_hex_word:
	or	r4, r3, 3
	mflr	5
	srwi	r3, r4, 28
	bl	put_hex
	srwi	r3, r4, 24
	bl	put_hex
	srwi	r3, r4, 20
	bl	put_hex
	srwi	r3, r4, 16
	bl	put_hex
	srwi	r3, r4, 12
	bl	put_hex
	srwi	r3, r4, 8
	bl	put_hex
	srwi	r3, r4, 4
	bl	put_hex
	or	r3, r4, 4
	bl	put_hex
	li	r3, 32
	bl	tgt_putchar
	mtlr	5
	blr

put_hex:
	andi.	r3, r3, 0xf
	lis	r9, HIADJ(hexchars)
	addi	r9, r9, LO(hexchars)
	add	r9, r9, r3
	add	r9, r9, r16
	lbz	r3, 0(r9)
	b	tgt_putchar

	.rodata
hexchars:
	.ascii	"0123456789abcdef"

	.text

initdbglednum:
	lis	r5, HIADJ(DBGLEDINIT)
	li	r3, 0x0f
	stw	r3, LO(DBGLEDINIT)(r5)
	blr

	.globl	dbglednum
dbglednum:
	lis	r5, HIADJ(DBGLED)
	nor	r3, r3, r3
	stw	r3, LO(DBGLED)(r5)
	stw	r3, LO(DBGLED)(r5)
	blr

/*
 *  Probe an SDRAM module for it's size. Returns size in Mbyte.
 *  Size is 'number of banks' * 'bank density' * 'number of module banks'
 */
probe_sdram_size:
#ifdef notyet
	mflr	r10
	andi.	r11, r3, 0x700		/* module address */
	bl	boot_i2c_read
	cmpwi	r3, -1
	beq	sdram_probe_err		/* no module found */

	ori	r3, r11, 5
	bl	boot_i2c_read		/* get number of module banks */
	or	r12, r3, r3

	ori	r3, r11, 31
	bl	boot_i2c_read		/* get bank density */
	mullw	r12, r12, r3

	ori	r3, r11, 17
	bl	boot_i2c_read		/* get number of banks */
	mullw	r12, r12, r3

	lis	r3, HI(0x100000)
	mullw	r3, r3, r12

	mtlr	r10
	blr

sdram_probe_err:
	li	r3, 0
	mtlr	r10
#endif
	blr