pld.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

#include <machine/endian.h>
/*
 * CP7000 PLD Registers 
 */

#ifndef _LOCORE
typedef struct {
    unsigned char revision;	/* Board Assembly Revision */
    unsigned char pld1id;	/* PLD 1 ID */
    unsigned char pld2id;	/* PLD 2 ID */
    unsigned char reset_stat;	/* Reset Status Register */
    unsigned char board_stat;	/* Board Status Register */
    unsigned char cpci_id;	/* Compact PCI ID Register */
    unsigned char reserved[2];	/* Reserved */
    unsigned char control;	/* Control Register */
    unsigned char cpu_eeprom;	/* CPU Configuration EEPROM Register */
    unsigned char intmask;	/* Interrupt Mask Register */
    unsigned char intstat;	/* Interrupt Status Register */
    unsigned char intset;	/* Interrupt Set Register */
    unsigned char intclr;	/* Interrupt Clear Register */
} plddev;

#endif

#define REVISION	0x0	/* Board Assembly Revision */
#define PLD1ID		0x1	/* PLD 1 ID */
#define PLD2ID		0x2	/* PLD 2 ID */
#define RESET_STAT	0x3	/* Reset Status Register */
#define BOARD_STAT	0x4	/* Board Status Register */
#define CPCI_ID		0x5	/* Compact PCI ID Register */
#define CONTROL		0x8	/* Control Register */
#define CPU_EEPROM	0x9	/* CPU Configuration EEPROM Register */
#define INTMASK		0xA	/* Interrupt Mask Register */
#define INTSTAT		0xB	/* Interrupt Status Register */
#define INTSET		0xC	/* Interrupt Set Register */
#define INTCLR		0xD	/* Interrupt Clear Register */

/* Reset Status Register */
#define	RESET_POWER	0x01	/* Power Up Reset */
#define	RESET_BUTTON	0x02	/* Push Button Reset */
#define	RESET_CPCI	0x04	/* Compact PCI Reset */
#define	RESET_WDOG	0x08	/* Watchdog Reset */
#define	RESET_SW	0x10	/* Software Reset */

/* Board Status Register */
#define	BOARD_USER	0x80	/* User Jumper Installed */
#define	BOARD_FWRITE	0x40	/* Flash Write Enable Jumper Installed */
#define	BOARD_RES0	0x20	/* Not used */
#define	BOARD_PHY	0x08	/* Transition Board PHY Active */
#define	BOARD_L3_NONE	0x00	/* No L3 Cache */
#define	BOARD_L3_2MB	0x04	/* 2MB L3 Cache */
#define	BOARD_L3_4MB	0x08	/* 4MB L3 Cache */
#define	BOARD_L3_8MB	0x0c	/* 8MB L3 Cache */
#define	BOARD_L3_MASK	0x0c	/* Mask bits */

#define BOARD_RAM_1GB	0x00	/* 1GB DRAM */	
#define BOARD_RAM_128MB	0x01	/* 128MB DRAM */	
#define BOARD_RAM_256MB	0x02	/* 256MB DRAM */	
#define BOARD_RAM_512MB	0x03	/* 512MB DRAM */	
#define BOARD_RAM_MASK	0x03	/* Mask bits */	

/* Compact PCI ID Register */
#define	CPCI_SSLOT	0x20	/* CPCI System Slot */
#define	CPCI_ADDR_MASK	0x1f	/* Mask bit for Geographical Address */

/* Control Register */
#define	CTRL_I2C_CLK	0x01	/* I2C Clock Line */
#define	CTRL_I2C_DAT	0x02	/* I2C Data I/O */
#define	CTRL_I2C_CLK_EN	0x04	/* I2C Enable Clock Line */
#define	CTRL_I2C_DAT_EN	0x08	/* I2C Enable Data I/O */
#define	CTRL_I2C_ST	0x10	/* I2C Data Latch Strobe */
#define	CTRL_L1_WDOG_EN	0x20	/* Enable Level 1 Watchdog */
#define	CTRL_L2_WDOG_EN	0x40	/* Enable Level 2 Watchdog */
#define	CTRL_L2_WDOG_ST	0x40	/* Level 2 Watchdog Strobe */

/* CPU Configuration EEPROM */
#define	EEPROM_CSEL	0x01	/* EEPROM Chip Select */
#define	EEPROM_CLK	0x02	/* EEPROM Clock */
#define	EEPROM_DAT_OUT	0x04	/* EEPROM Data Output */
#define	EEPROM_DAT_IN	0x08	/* EEPROM Data Input */
#define	EEPROM_STROBE	0x10	/* EEPROM Read Strobe */

/* Interrupt Mask Register */
#define	INTMASK_INTA	0x01	/* CompactPCI INTA# Mask */
#define	INTMASK_INTB	0x02	/* CompactPCI INTB# Mask */
#define	INTMASK_INTC	0x04	/* CompactPCI INTC# Mask */
#define	INTMASK_INTD	0x08	/* CompactPCI INTD# Mask */
#define	INTMASK_BRIDGE	0x10	/* I21554/I21555 Secondary Interrupt Mask */
#define	INTMASK_ENUM	0x20	/* CompactPCI ENUM# Mask */
#define	INTMASK_DEG	0x40	/* CompactPCI DEG# Mask */
#define	INTMASK_FAL	0x80	/* CompactPCI FAL# Mask */

/* Interrupt Status Register */
#define	INTSTAT_INTA	INTMASK_INTA	/* CompactPCI INTA# Status */
#define	INTSTAT_INTB	INTMASK_INTB	/* CompactPCI INTB# Status */
#define	INTSTAT_INTC	INTMASK_INTC	/* CompactPCI INTC# Status */
#define	INTSTAT_INTD	INTMASK_INTD	/* CompactPCI INTD# Status */
#define	INTSTAT_BRIDGE	INTMASK_BRIDGE	/* I21554/I21555 Secondary Interrupt Status */
#define	INTSTAT_ENUM	INTMASK_ENUM	/* CompactPCI ENUM# Status */
#define	INTSTAT_DEG	INTMASK_ENUM	/* CompactPCI DEG# Status */
#define	INTSTAT_FAL	INTMASK_FAL	/* CompactPCI FAL# Status */

/* Interrupt Set */
#define	INTSET_INTA	INTMASK_INTA	/* CompactPCI INTA# Set */
#define	INTSET_INTB	INTMASK_INTB	/* CompactPCI INTB# Set */
#define	INTSET_INTC	INTMASK_INTC	/* CompactPCI INTC# Set */
#define	INTSET_INTD	INTMASK_INTD	/* CompactPCI INTD# Set */
#define	INTSET_ULED	0x40		/* USER LED On */
#define	INTSET_BLED	0x80		/* BIT LED On */

/* Interrupt Clear Register */
#define	INTCLR_INTA	INTMASK_INTA	/* CompactPCI INTA# Clear */
#define	INTCLR_INTB	INTMASK_INTB	/* CompactPCI INTB# Clear */
#define	INTCLR_INTC	INTMASK_INTC	/* CompactPCI INTC# Clear */
#define	INTCLR_INTD	INTMASK_INTD	/* CompactPCI INTD# Clear */
#define	INTCLR_ULED	INTSET_ULED	/* USER LED Off */
#define	INTCLR_BLED	INTSET_BLED	/* BIT LED Off */

#define PLDREG(x)	(PLD_BASE_ADDR + x)