pci_machdep.c

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$Id: pci_machdep.c,v 1.1 2002/01/16 13:45:33 pefo Exp $ */

/*
 * Copyright (c) 2000-2001 Opsycon AB  (www.opsycon.se)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Opsycon AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */
#include <sys/param.h>
#include <sys/device.h>
#include <sys/systm.h>

#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>

#include <machine/pio.h>

#include "target/power7e.h"

#include <pmon.h>

/* PCI i/o regions in PCI space */
#define PCI_IO_SPACE_PCI_BASE		0x00000000

/* PCI mem regions in PCI space */
#define PCI_LOCAL_MEM_PCI_BASE	0x00000000	/* CPU Mem accessed from PCI */

/* soft versions of above */
static pcireg_t pci_local_mem_pci_base;


extern int _pciverbose;
extern void *pmalloc __P((size_t ));

static struct pci_bus *_pci_bus[16];
static int _max_pci_bus = 0;

/*
 * Called to initialise the bridge at the beginning of time
 */
int
_pci_hwinit(initialise, iot, memt)
	int initialise;
	bus_space_tag_t iot;
	bus_space_tag_t memt;
{
        pcireg_t stat;
	struct pci_device *pd;
	struct pci_bus *pb;

	stat = 0;

        /*
         *  PCI and local bus maps 1-1
         */
        iot->bus_base = PA_TO_VA(CPC700_PCI_IO_BASE);
        iot->bus_reverse = 1;
        memt->bus_base = PA_TO_VA(0);
        memt->bus_reverse = 1;

	/* Where PCI finds our RAM memory in the PCI map */
        pci_local_mem_pci_base = PCI_LOCAL_MEM_PCI_BASE;

	if (!initialise) {
		return(0);
	}

	/*
	 * Initialize PCI Head device (Northbridge).
	 */
	pd = pmalloc(sizeof(struct pci_device));
	if(pd == NULL) {
		printf("pci: can't alloc memory for northbridge\n");
		return(-1);
	}

	pd->pa.pa_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
	pd->pa.pa_iot = iot;
	pd->pa.pa_memt = memt;
	pd->pa.pa_dmat = &bus_dmamap_tag;
	_pci_head = pd;

	pd->bridge.secbus = pmalloc(sizeof(struct pci_bus));
	if(pd->bridge.secbus == NULL) {
		printf("pci: can't alloc memory for new pci bus\n");
		return(-1);
	}

	pb = pd->bridge.secbus;
	pb->max_lat = 255;
	pb->fast_b2b = 1;
	pb->prefetch = 1;
	pb->bandwidth = 4000000;
	pb->ndev = 1;
	_pci_bushead = pb;
	_pci_bus[0] = pb;
	_max_pci_bus = 1;

	pb->minpcimemaddr = PCI_MEM_SPACE_BASE;
	pb->nextpcimemaddr = PCI_MEM_SPACE_BASE + PCI_MEM_SPACE_SIZE;

	pb->minpciioaddr = PCI_IO_SPACE_BASE;
	pb->nextpciioaddr = PCI_IO_SPACE_BASE + PCI_IO_SPACE_SIZE;
	pb->pci_io_base = CPC700_PCI_IO_BASE;

	/* Set up PCI to local memory PMM0 to a 1-1 mapping */
	out32rb(CPC700_PMM0HIGH, 0x00000000);
	out32rb(CPC700_PMM0LO,   0x80000000);
	out32rb(CPC700_PMM0ADDR, 0x80000000);
	out32rb(CPC700_PMM0MASK, 0xf0000001);

	out32rb(CPC700_PMM1HIGH, 0x00000000);
	out32rb(CPC700_PMM1LO,   0x10000000);
	out32rb(CPC700_PMM1ADDR, 0x90000000);
	out32rb(CPC700_PMM1MASK, 0xf0000001);

	out32rb(CPC700_PMM2HIGH, 0x00000000);
	out32rb(CPC700_PMM2LO,   0x00000000);
	out32rb(CPC700_PMM2ADDR, 0x00000000);
	out32rb(CPC700_PMM2MASK, 0x00000000);

	/* PTM1 maps to entire internal memory */
	out32rb(CPC700_PTM1ADDR, 0x00000000);
	out32rb(CPC700_PTM1SIZE, 0xc0000001);		/* Allow 1GB */
	out32rb(CPC700_PCICFGADDR, CPC700_PCIPTM1BAR);
	out32rb(CPC700_PCICFGDATA, 0x00000008);

	/* Disable PTM2 */
	out32rb(CPC700_PTM2SIZE,   0x00000001);
	out32rb(CPC700_PTM2ADDR,   0x00000000);
	out32rb(CPC700_PCICFGADDR, CPC700_PCIPTM2BAR);
	out32rb(CPC700_PCICFGDATA, 0x00000000);
	out32rb(CPC700_PTM2SIZE,   0x00000000);

        if (!initialise) {
                return(0);
        }

        return(1);
}


/*
 * Called to reinitialise the bridge after we've scanned each PCI device
 * and know what is possible.
 */
void
_pci_hwreinit (void)
{
}

void
_pci_flush (void)
{
}


/*
 *  Map the CPU virtual address of an area of local memory to a PCI
 *  address that can be used by a PCI bus master to access it.
 */
vm_offset_t
_pci_dmamap(va, len)
	vm_offset_t va;
	unsigned int len;
{
	return(pci_local_mem_pci_base + VA_TO_PA (va));
}

/*
 *  Map the PCI address of an area of local memory to a CPU physical
 *  address.
 */
vm_offset_t
_pci_cpumap(pcia, len)
	vm_offset_t pcia;
	unsigned int len;
{
	return PA_TO_VA(pcia - pci_local_mem_pci_base);
}

int
_pci_canscan (pcitag_t tag)
{
	int bus, device, function;

	_pci_break_tag (tag, &bus, &device, &function);
	if(bus == 0 && device == 0) {
		return(0);		/* Ignore CPC700 */
	}
	return (1); 
}

void *
_pci_map_int(tag, level, func, arg)
	pcitag_t tag;
	int level;
	int (*func) __P((void *));
	void *arg;
{
	pcireg_t data;
	int pin, bus, device;

	data = _pci_conf_read(tag, PCI_INTERRUPT_REG);

	pin = PCI_INTERRUPT_PIN(data);

	if (pin == 0) {
		/* No IRQ used. */
		return NULL;
	}

	if (pin > 4) {
		if (_pciverbose >= 1) {
			_pci_tagprintf (tag, "_pci_map_int: bad interrupt pin %d\r\n", pin);
		}
		return(NULL);
	}


	_pci_break_tag (tag, &bus, &device, NULL);

	if (bus != 0 || device > 5) {
		return(NULL);
	}

	/* XXX need to work this out based on device number etc. */
	_pci_tagprintf(tag, "_pci_map_int: attempt to map device %d pin %c\n", 
		   device, '@' + pin);
	return(NULL);
}