start.s

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$Id: start.S,v 1.5 2002/11/07 15:05:27 pefo Exp $ */

/*
 * Copyright (c) 2000 Opsycon AB  (www.opsycon.se)
 * Copyright (c) 2000 Rtmx, Inc   (www.rtmx.com)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed for Rtmx, Inc by
 *	Opsycon Open System Consulting AB, Sweden.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#include "target/pmon_target.h"

#include <pmon/dev/ns16550.h>

#define	HID0	1008
#define	L2CR	1017
#define	CTR	9

#define HIADJ(x)	(x)@ha
#define HI(x)		(x)@h
#define LO(x)		(x)@l

/*
 *  Macros used to setup CPC700 memory control.
 */

#define PRINTSTR(str)           \
	bl	9f;             \
	.asciz	str;            \
	.align	2;              \
9:	mflr	3;             \
	bl	serial_out 

#ifdef BOOT_TRACE
#define DBGPRINTSTR(str)        PRINTSTR(str)
#else
#define DBGPRINTSTR(str)
#endif 

/*
 *  Register usage throughout code.
 *
 *	r0
 *	r1
 *	r2	CPC700 address reg pointer
 *	r3	CPC700 data reg pointer
 *	r4	Scratch for register updates
 *	r5
 *	r1
 *	r15	Memory size after probing
 *	r16	Link load offset
 *	r26	CPC700 revision
 *	r28	Processor type
 *	r1
 */

	.space	0x100

	.globl	_start
	.globl	start
_start:
start:

	.globl	pmon_stack
stack = start - 0x4000		/* Place PMON stack below PMON start in RAM */
pmon_stack = start		/* Top of stack */
	.globl	pmon_intstack
intstack = stack - 0x2000	/* 8k PMON interrupt stack */
pmon_intstack = stack		/* Top of stack */

/* Clear MSR to diable interrupts and checks */

/* Turn off translations and clear mapping registers */

	li	1, 0x0
	mtmsr	1		/* Clear MSR */

	mtibatu	0, 1
	mtibatl	0, 1
	mtibatu	1, 1
	mtibatl	1, 1
	mtibatu	2, 1
	mtibatl	2, 1
	mtibatu	3, 1
	mtibatl	3, 1
	mtdbatu	0, 1
	mtdbatl	0, 1
	mtdbatu	1, 1
	mtdbatl	1, 1
	mtdbatu	2, 1
	mtdbatl	2, 1
	mtdbatu	3, 1
	mtdbatl	3, 1
	isync
	sync
	sync
	lis	1, 0x8000
	isync
	mtsr	0, 1
	mtsr	1, 1
	mtsr	2, 1
	mtsr	3, 1
	mtsr	4, 1
	mtsr	5, 1
	mtsr	6, 1
	mtsr	7, 1
	mtsr	8, 1
	mtsr	9, 1
	mtsr	10, 1
	mtsr	11, 1
	mtsr	12, 1
	mtsr	13, 1
	mtsr	14, 1
	mtsr	15, 1
	isync
	sync
	sync

/* Turn off caches (if we got here softloaded) */

	mfspr   3, HID0
	isync
	rlwinm  4, 3, 0, 18, 15	/* clear d15 and d16 */
	sync
	isync
	mtspr   HID0, 4 	/* turn off caches */
	isync

	mfspr	4, L2CR
	lis	3, 0x8000
	andc.	4, 4, 3
	mtspr	L2CR, 4
	isync


/* Get CPU type */
	mfspr	28, 287
	rlwinm	28, 28, 16, 16, 31

/* Set r16 to the load vs link offset. */
	bl	1f
1:
	mflr	3
	lis	16, 0xffff
	and.	16, 16, 3
	lis	4, HI(start)
	sub	16, 16, 4		/* R16 is now load offset */

/*
 *  Find out if executing in ROM or RAM. Note memory size wired to 64Mb.
 */
	lis	15, 0x0400		/* Memory size accumulator = 64MB */
	lis	4, 0xf000		/* Last 256Mb segment */
	and.	4, 4, 3
	beq	in_ram			/* We are ram loaded! */

/*
 *  Init the PCI/Memory controller (CPC700)
 */
	lis	0, HI(CPC700_PCICFGADDR)
	ori	1, 0, 0x0000
	ori	2, 0, 0x0004
/**/
	lis	3, 0x8000
	ori	3, 3, CPC700_PCI_REV
	stwbrx	3, 0, 1
	IORDER
	lwbrx	26, 0, 2		/* Get device revision number */
	andi. 	26, 26, 0x00ff		/* Isolate revision bits. */
/**/
	lis	3, 0x8000
	ori	3, 3, CPC700_PCI_CMD
	stwbrx	3, 0, 1
	IORDER
	lhbrx	4, 0, 2
	lis	3, 0x001f		/* Enable and reset pci status */
	ori	3, 3, 0xfc00
	and	4, 4, 3
	lis	3, 0xf900
	ori	3, 3, 0x0106
	or	4, 4, 3
	sthbrx	4, 0, 2			/* XXX Check size of store... */
	IORDER

/*
 * Set up CPC700's memory configuration as follows:
 *
 *             Starting        Ending
 *	Bank 0 (FFC00000 -- FFF00000) -- Boot ROM (8-bit)
 *	Bank 1 (00000000 -- xxxx0000) -- SDRAM bank 0
 *	Bank 2 (xxxxxxxx -- xxxxxxxx) -- SDRAM bank 1
 *	Bank 3 (xxxxxxxx -- xxxxxxxx) -- SDRAM bank 2
 *	Bank 4 (xxxxxxxx -- xxxxxxxx) -- SDRAM bank 3
 */
	lis	0, HI(CPC700_MEMCFGADDR)
	ori	1, 0, LO(CPC700_MEMCFGADDR)
	ori	2, 0, LO(CPC700_MEMCFGDATA)
/**/
	/* Bank 0 - Flash etc. */
	CPC700_MEM_SETUP(CPC700_MBEN,    0x80000000, 0x07ffffff)
	CPC700_MEM_SETUP(CPC700_FWEN,    0x80000000, 0x000fffff)
	CPC700_MEM_SETUP(CPC700_MB0SA,   0xff800000, 0x000fffff)
	CPC700_MEM_SETUP(CPC700_MB0EA,   0xfff00000, 0x000fffff)
	CPC700_MEM_SETUP(CPC700_RPB0P,   0x3c000000, 0x03ffffff) /* Wait states... */

	lis	5, HIADJ(P7E_FBMISC)
	lbz	4, LO(P7E_FBMISC)(5)
	andi.	4, 4, LO(~(P7E_BITF|P7E_ULED2|P7E_ULED1))
	stb	4, LO(P7E_FBMISC)(5)

	CPC700_MEM_SETUP(CPC700_MEMTYPE, 0x15400000, 0x003fffff)
	CPC700_MEM_SETUP(CPC700_DAM,     0x15400000, 0x003fffff)
	CPC700_MEM_SETUP(CPC700_RBW,     0x00000000, 0x003fffff)
	CPC700_MEM_SETUP(CPC700_RTR,     0x03f80000, 0x0000ffff)
	CPC700_MEM_SETUP(CPC700_SDTR1,   0x00049c0a, 0xfe0003e0)
	CPC700_MEM_SETUP(CPC700_ECCCF,   0x40600000, 0x370707ff)

	/* Look at memory configuration */
	CPC700_MEM_SETUP(CPC700_MB1SA,   0x00000000, 0x000fffff)
	lis	5, HIADJ(P7E_MEM_CFG)
	lbz	4, LO(P7E_MEM_CFG)(5)
	andi.	4, 4, 0xc0		/* Baseboard bits. */
	lis	15, 0x0400		/* 64MB */
	cmpwi	4, 0x80
	beq	1f
	lis	15, 0x0800		/* 128MB */
	cmpwi	4, 0x40
	beq	1f
	lis	15, 0x1000		/* 256MB */
	cmpwi	4, 0x00
	bne	bootinit_abort		/* No memory? */

	CPC700_MEM_SETUP(CPC700_DAM,    0x20000000, 0xcfffffff)

1:
	lis	4, 0x0010
	sub	4, 15, 4		/* Adjust end address */
	CPC700_MEM_RSETUP(CPC700_MB1EA,  4)
	CPC700_MEM_SETUP(CPC700_MBEN,	0x40000000, 0xbfffffff)

	lis	5, HIADJ(P7E_MEM_CFG)
	lbz	3, LO(P7E_MEM_CFG)(5)
	andi.	3, 3, 0x0f		/* module 1 bits. */
	lis	4, 0x0400		/* 64MB */
	cmpwi	3, 0x0e
	beq	1f
	lis	4, 0x0800		/* 128MB */
	cmpwi	3, 0x0d
	beq	1f
	cmpwi	3, 0x0c
	bne	2f

	CPC700_MEM_SETUP(CPC700_DAM,	0x08000000, 0xf3ffffff)
	lis	4, 0x1000		/* 256MB, change address mode */
1:
	CPC700_MEM_RSETUP(CPC700_MB2SA,  15)
	add	15, 15, 4
	lis	4, 0x0010
	sub	4, 15, 4		/* Adjust end address */
	CPC700_MEM_RSETUP(CPC700_MB2EA,  4)
	CPC700_MEM_SETUP(CPC700_MBEN,    0x20000000, 0xdfffffff)

#ifdef TWOEXTRAMEMMODULES
2:
	lis	5, HIADJ(P7E_MEM_CFG)
	lbz	3, LO(P7E_MEM_CFG)(5)
	andi.	3, 3, 0x0f			/* module 2 bits. */
	lis	4, 0x0400		/* 64MB */
	cmpwi	3, 0x0e
	beq	1f
	lis	4, 0x0800		/* 128MB */
	cmpwi	3, 0x0d
	beq	1f
	lis	4, 0x1000		/* 256MB */
	cmpwi	3, 0x0c
	bne	2f

1:
	CPC700_MEM_RSETUP(CPC700_MB3SA,  15)
	add	15, 15, 4
	lis	4, 0x0010
	sub	4, 15, 4		/* Adjust end address */
	CPC700_MEM_RSETUP(CPC700_MB3EA,  4)
	CPC700_MEM_SETUP(CPC700_MBEN,    0x10000000, 0xefffffff)
#endif

2:
	CPC700_MEM_SETUP(CPC700_MCOPT1,  0x85000000, 0x18ffffff)
/**/
/**/
	li	4, 0x2000
	mtctr	4
1:
	bdnz	1b		/* Delay to allow memory to initialize */
/**/
	mfmsr	3
	ori	3, 3, 0x3002	/* set FP, ME and RI */
	mtmsr	3

	PRINTSTR("\r\nPMON2000 PowerPC Initializing. Standby...\r\n")

/* Set up PCI to local mapping. FFF0-> now readable so use a table. */
	bl	init_pmm

	.long	CPC700_PMM0HIGH, 0x00000000
	.long	CPC700_PMM0LO,   0x00000000
	.long	CPC700_PMM0ADDR, 0x80000000
	.long	CPC700_PMM0MASK, 0xf0000001
	.long	CPC700_PMM1HIGH, 0x00000000
	.long	CPC700_PMM1LO,   0x10000000
	.long	CPC700_PMM1ADDR, 0x90000000
	.long	CPC700_PMM1MASK, 0xf0000001

	.long	CPC700_PTM1ADDR, 0x00000000
	.long	CPC700_PTM1SIZE, 0xf0000001
	.long	CPC700_PTM2ADDR, 0x00000000
	.long	CPC700_PTM2SIZE, 0x00000000

	.long	CPC700_PCICFGADDR, 0x80000000+0x14
	.long	CPC700_PCICFGADDR+4, 0x00000008
	.long	0

init_pmm:
	mflr	5
	lwz	3, 0(5)		/* address */
1:
	lwz	4, 4(5)		/* value */
	stwbrx	4, 0, 3
	addi	5, 5, 2*4
	lwz	3, 0(5)
	and.	3, 3, 3
	bne	1b

	DBGPRINTSTR("PCI mapping done!\r\n")

#if 0
/*
 *  We init the IIC interface here, although doing it in C is an option.
 *  However one day we may need to read SPD memory os SDRAM modules...
 */
	lis	3, HIADJ(CPC700_IIC0)
	addi	3, 3, LO(CPC700_IIC0)

	li	4, 0x0
	stb	4, IIC_LMADR(3)
	stb	4, IIC_HMADR(3)
	stb	4, IIC_LSADR(3)
	stb	4, IIC_HSADR(3)
	li	4, 0x8
	stb	4, IIC_STS(3)
	li	4, 0x8f
	stb	4, IIC_EXTSTS(3)
	li	4, 0x3
	stb	4, IIC_CLKDIV(3)
	li	4, 0x0
	stb	4, IIC_INTRMSK(3)
	stb	4, IIC_XFRCNT(3)
	li	4, 0xf0
	stb	4, IIC_XTCNTLSS(3)
	li	4, 0x43
	stb	4, IIC_MDCNTL(3)
	li	4, 0x0
	stb	4, IIC_CNTL(3)

	DBGPRINTSTR("IIC setup done!\r\n")
#endif

/*
 *  RAM memory should now be operational, we can call C-code (some
 *  restrictions still do apply, like usage of initialised vars).
 *  We scrub the entire memory to get rid of potential parity errors.
 */
#ifdef BOOT_TRACE
	PRINTSTR("Memory controller configuration\r\n")
	lis	0, HI(CPC700_MEMCFGADDR)
	ori	1, 0, LO(CPC700_MEMCFGADDR)
	ori	2, 0, LO(CPC700_MEMCFGDATA)

	li	7, 0
1:
	stw	7, 0(1)
	IORDER
	lwz	3, 0(2)

	bl	put_hex_word
	addi	7, 7, 4
	cmpwi	7, 0x100
	beq	2f
	andi.	3, 7, 0x1f
	bne	1b
	PRINTSTR("\r\n")
	b	1b

2:
	PRINTSTR("\r\n")
#endif

/*
 *  Do a simple memory test to chek that memory is there.
 */
	li	4, 0
1:
	stw	4, 0(4)
	addi	4, 4, 4
	cmpwi	4, 0x2000
	bne	1b

	li	4, 0
2:
	lwz	3, 0(4)
	cmpw	3, 4
	bne	memt_fail
	addi	4, 4, 4
	cmpwi	4, 0x2000
	bne	2b

	lis	3, 0x10			/* 1MB */
	li	4, 0x4000		/* Start from 0x4000 to preserve */
	sub	3, 3, 4			/* message areas */
	srwi	3, 3, 2		
	mtctr	3
1:
	stw	4, 0(4)			/* Zero out what will be the stack */
	addic	4, 4, 0x4
	bdnz	1b

	DBGPRINTSTR("Memory clean done!\r\n")
	b	copydown

in_ram:
	PRINTSTR("\r\nPMON2000 PowerPC Ramloaded. Standby...\r\n")
#ifdef BOOT_TRACE
	PRINTSTR("Memory controller configuration\r\n")
	lis	0, HI(CPC700_MEMCFGADDR)
	ori	1, 0, LO(CPC700_MEMCFGADDR)
	ori	2, 0, LO(CPC700_MEMCFGDATA)

	li	7, 0
1:
	stw	7, 0(1)
	IORDER
	lwz	3, 0(2)

	bl	put_hex_word
	addi	7, 7, 4
	cmpwi	7, 0x100
	beq	2f
	andi.	3, 7, 0x1f
	bne	1b
	PRINTSTR("\r\n")
	b	1b

2:
	PRINTSTR("\r\n")
#endif

copydown:

	lis	4, HI(start)
	addi	1, 4, -64		/* RAM START++ will be overwritten */
	stw	15, 8(1)		/* Save away memory size */

	add	3, 4, 16
	bl	copytoram		/* Go do PPC initialization */

	cmpwi	3, 0
	beq	__go			/* Verify after copy succeded */

	PRINTSTR("PANIC! Verify after copy to ram failed!\r\n")
	b	bootinit_fail
/*
 *  All stations are GO for takeoff.
 *  Lets go to the other end of the universe!
 */
__go:
	DBGPRINTSTR("copytoram OK!\r\n")

	lwz	3, 8(1)			/* Memorysize */

#if 0
	mfspr	4, HID0	
	ori	4, 4, 0x0084
	isync			/* Serialize disable and branch history enab */
	mtspr	HID0, 4	
	isync
#endif

	lis	1, HIADJ(STACKBASE)
	addi	1, 1, LO(STACKBASE)
	mtsprg	0, 1
	addi	1, 1, STACKSIZE-64
	li	0, 0x0		/* Mark end of frames on stack */
	stw	0, 0(1)
	stw	0, 4(1)

	lis	4, HIADJ(initppc)
	addi	4, 4, LO(initppc)
	mtlr	4
	blr

/**/
memt_fail:
	or	7, 4, 4
	or	3, 4, 4
	bl	put_hex_word
	PRINTSTR("\r\n")
	addi	8, 7, 0x100
1:
	lwz	3, 0(7)

	bl	put_hex_word
	addi	7, 7, 4
	cmpw	7, 8
	beq	2f
	sub	3, 8, 7
	andi.	3, 3, 0x1f
	bne	1b
	PRINTSTR("\r\n")
	b	1b

2:
	PRINTSTR("\r\nWoah! Simple memtest failed!\r\n")

bootinit_abort:
	PRINTSTR("PMON2000 PowerPC ABORT! No RAM memory found!\r\n")

bootinit_fail:
1:
	lis	5, HIADJ(P7E_FBMISC)
	lbz	4, LO(P7E_FBMISC)(5)
	xori	4, 4, P7E_BITF
	stb	4, LO(P7E_FBMISC)(5)

	lis	1, 1
	mtctr	1
2:
	bdnz	2b

	b	1b

/**/

/*
 *  Simple serial output routine used to communicate messages
 *  during prom setup before 'real' driver is running.
 *  This code simply displays a string of chars on the console.
 */

serial_out:
	lis	30, HIADJ(COM1_BASE_ADDR)
	addi	30, 30, LO(COM1_BASE_ADDR)
	li	31, 1
	stb	31, 4(30)	/* DTR on */
	IORDER
	li	31, 0x80	/* Get to divisor latch */
	stb	31, 3(30)
	IORDER
	li	31, NS16550HZ/(16*CONS_BAUD)
	stb	31, 0(30)
	IORDER
	li	31, 0x0
	stb	31, 1(30)
	IORDER
	li	31, 0x3		/* 8 bits no parity */
	stb	31, 3(30)
	IORDER

2:
	lbz	31, 0(3)
	cmpwi	31, 0
	beq	4f
3:
	lbz	31, 5(30)
	andi.	31, 31, 0x20
	beq	3b		/* Wait for tx buffer empty */

	lbz	31, 0(3)
	stb	31, 0(30)	/* send char */
	IORDER
	addi	3, 3, 1
	b	2b

4:
	blr			/* return */
/**/

	.globl	tgt_putchar
tgt_putchar:
	lis	9, HIADJ(COM1_BASE_ADDR)
	addi	9, 9, LO(COM1_BASE_ADDR)
1:
	lbz	0, 5(9)
	andi.	0, 0, 0x20
	beq	1b

	stb	3, 0(9)
	blr
/**/

put_hex_word:
	or	4, 3, 3
	mflr	5
	srwi	3, 4, 28
	bl	put_hex
	srwi	3, 4, 24
	bl	put_hex
	srwi	3, 4, 20
	bl	put_hex
	srwi	3, 4, 16
	bl	put_hex
	srwi	3, 4, 12
	bl	put_hex
	srwi	3, 4, 8
	bl	put_hex
	srwi	3, 4, 4
	bl	put_hex
	or	3, 4, 4
	bl	put_hex
	li	3, 32
	bl	tgt_putchar
	mtlr	5
	blr

put_hex:
	andi.	3, 3, 0xf
	lis	9, HIADJ(hexchars)
	addi	9, 9, LO(hexchars)
	add	9, 9, 3
	add	9, 9, 16
	lbz	3, 0(9)
	b	tgt_putchar

	.rodata
hexchars:
	.ascii	"0123456789abcdef"

	.text