rm9k.h

MIPS处理器的bootloader,龙芯就是用的修改过的PMON2

/*	$Id: rm9k.h,v 1.2 2003/07/08 20:39:53 pefo Exp $ */

/*
 * Copyright (c) 2003 Opsycon AB  (www.opsycon.se)
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Opsycon AB.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#if !defined(_RM9K_H_)
#define _RM9K_H_

/*
 *  Config stream registers
 */
#define	RM9K_CONF000	0x00e0
#define	RM9K_CONF032	0x00e4
#define	RM9K_CONF064	0x00e8
#define	RM9K_CONF096	0x00ec
#define	RM9K_CONF128	0x00d0
#define	RM9K_CONF160	0x00d4
#define	RM9K_CONF192	0x00d8
#define	RM9K_CONF224	0x00dc

/* CPU reset register */
#define	RM9K_RSTSTAT	0x0a20
#define	RM9K_RSTSET	0x0a24
#define	RM9K_RSTCLR	0x0a28

/* Semaphore register */
#define	RM9K_SEM	0x0a60
#define	RM9K_SEMSET	0x0a64
#define	RM9K_SEMCLR	0x0a68


#endif