📄 ep7312.h
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/*------------------------------------------------------------------------------------------------------------------
* ep7312.h --
*
*
*
------------------------------------------------------------------------------------------------------------------*/
#ifndef __H_EP7312__
#define __H_EP7312__
#include "frmwrk.h" //
//为了C++语言中兼容。
#ifdef __cplusplus
extern "C" {
#endif
/*---------------------------------------------------------------------------------------------------------------
* Interface macro & data definition
---------------------------------------------------------------------------------------------------------------*/
//ID
#define rUNIQID (*(volatile u32 *)(SFR_BADDR + 0X2440))
#define rRANDID0 (*(volatile u32 *)(SFR_BADDR + 0x2700))
#define rRANDID1 (*(volatile u32 *)(SFR_BADDR + 0x2704))
#define rRANDID2 (*(volatile u32 *)(SFR_BADDR + 0x2708))
#define rRANDID3 (*(volatile u32 *)(SFR_BADDR + 0x270c))
//System Register
#define rSYSCON1 (*(volatile u32 *)(SFR_BADDR + 0x0100))
#define rSYSFLG1 (*(volatile u32 *)(SFR_BADDR + 0x0140))
#define rSYSCON2 (*(volatile u32 *)(SFR_BADDR + 0x1100))
#define rSYSFLG2 (*(volatile u32 *)(SFR_BADDR + 0x1140))
#define rSYSCON3 (*(volatile u32 *)(SFR_BADDR + 0x2200))
#define rSTFCLR (*(volatile u32 *)(SFR_BADDR + 0x05c0))
#define rHALT (*(volatile u32 *)(SFR_BADDR + 0x0800))
#define rSTDBY (*(volatile u32 *)(SFR_BADDR + 0x0840))
#define rPLLW (*(volatile u32 *)(SFR_BADDR + 0x2610))
#define rPLLR (*(volatile u32 *)(SFR_BADDR + 0xa5a8))
//Memory Register
#define rMEMCFG1 (*(volatile u32 *)(SFR_BADDR + 0x0180))
#define rMEMCFG2 (*(volatile u32 *)(SFR_BADDR + 0x01c0))
#define rSDCONF (*(volatile u32 *)(SFR_BADDR + 0x2300))
#define rSDRFPR (*(volatile u32 *)(SFR_BADDR + 0x2340))
//Interrupt Register
#define rINTSR1 (*(volatile u32 *)(SFR_BADDR + 0x0240))
#define rINTMR1 (*(volatile u32 *)(SFR_BADDR + 0x0280))
#define rINTSR2 (*(volatile u32 *)(SFR_BADDR + 0x1240))
#define rINTMR2 (*(volatile u32 *)(SFR_BADDR + 0x1280))
#define rINTSR3 (*(volatile u32 *)(SFR_BADDR + 0x2240))
#define rINTMR3 (*(volatile u32 *)(SFR_BADDR + 0x2280))
//EOI
#define rBLEOI (*(volatile u32 *)(SFR_BADDR + 0x0600))
#define rMCEOI (*(volatile u32 *)(SFR_BADDR + 0x0640))
#define rTEOI (*(volatile u32 *)(SFR_BADDR + 0x0680))
#define rTC1EOI (*(volatile u32 *)(SFR_BADDR + 0x06c0))
#define rTC2EOI (*(volatile u32 *)(SFR_BADDR + 0x0700))
#define rRTCEOI (*(volatile u32 *)(SFR_BADDR + 0x0740))
#define rUMSEOI (*(volatile u32 *)(SFR_BADDR + 0x0780))
#define rCOEOI (*(volatile u32 *)(SFR_BADDR + 0x07c0))
#define rKBDEOI (*(volatile u32 *)(SFR_BADDR + 0x1700))
//GPIO
#ifdef __BIG_ENDIAN
#define rPADR (*(volatile u8 *)(SFR_BADDR + 0x0003))
#define rPADDR (*(volatile u8 *)(SFR_BADDR + 0x0043))
#define rPBDR (*(volatile u8 *)(SFR_BADDR + 0x0002))
#define rPBDDR (*(volatile u8 *)(SFR_BADDR + 0x0042))
#define rPDDR (*(volatile u8 *)(SFR_BADDR + 0x0000))
#define rPDDDR (*(volatile u8 *)(SFR_BADDR + 0x0040))
#define rPEDR (*(volatile u8 *)(SFR_BADDR + 0x0083))
#define rPEDDR (*(volatile u8 *)(SFR_BADDR + 0x00c3))
#else
#define rPADR (*(volatile u8 *)(SFR_BADDR + 0x0000))
#define rPADDR (*(volatile u8 *)(SFR_BADDR + 0x0040))
#define rPBDR (*(volatile u8 *)(SFR_BADDR + 0x0001))
#define rPBDDR (*(volatile u8 *)(SFR_BADDR + 0x0041))
#define rPDDR (*(volatile u8 *)(SFR_BADDR + 0x0003))
#define rPDDDR (*(volatile u8 *)(SFR_BADDR + 0x0043))
#define rPEDR (*(volatile u8 *)(SFR_BADDR + 0x0080))
#define rPEDDR (*(volatile u8 *)(SFR_BADDR + 0x00c0))
#endif
//UART
#define rUARTDR1 (*(volatile u32 *)(SFR_BADDR + 0x0480))
#define rUBRLCR1 (*(volatile u32 *)(SFR_BADDR + 0x04c0))
#define rUARTDR2 (*(volatile u32 *)(SFR_BADDR + 0x1480))
#define rUBRLCR2 (*(volatile u32 *)(SFR_BADDR + 0x14c0))
//SSI
#define rSYNCIO (*(volatile u32 *)(SFR_BADDR + 0x0500))
#define rSS2DR (*(volatile u32 *)(SFR_BADDR + 0x1500))
#define rSRXEOF (*(volatile u32 *)(SFR_BADDR + 0x1600))
#define rSS2POP (*(volatile u32 *)(SFR_BADDR + 0x16c0))
//Timer
#define rTC1D (*(volatile u32 *)(SFR_BADDR + 0x0300))
#define rTC2D (*(volatile u32 *)(SFR_BADDR + 0x0340))
//LCD
#define rLCDCON (*(volatile u32 *)(SFR_BADDR + 0x02c0))
#define rPALLSW (*(volatile u32 *)(SFR_BADDR + 0x0540))
#define rPALMSW (*(volatile u32 *)(SFR_BADDR + 0x0580))
#define rFBADDR (*(volatile u32 *)(SFR_BADDR + 0x1000))
//RTC
#define rRTCDR (*(volatile u32 *)(SFR_BADDR + 0x0380))
#define rRTCMR (*(volatile u32 *)(SFR_BADDR + 0x03c0))
//DAI
#define rDAIR (*(volatile u32 *)(SFR_BADDR + 0x2000))
#define rDAIR0 (*(volatile u32 *)(SFR_BADDR + 0x2040))
#define rDAIDR1 (*(volatile u32 *)(SFR_BADDR + 0x2080))
#define rDAIDR2 (*(volatile u32 *)(SFR_BADDR + 0x20c0))
#define rDAISR (*(volatile u32 *)(SFR_BADDR + 0x2100))
#define rDAI64Fs (*(volatile u32 *)(SFR_BADDR + 0x2600))
//Others
#define rPMPCON (*(volatile u32 *)(SFR_BADDR + 0x0400))
#define rCODR (*(volatile u32 *)(SFR_BADDR + 0x0440))
#define rLEDFLSH (*(volatile u32 *)(SFR_BADDR + 0x22c0))
//NAND Flash
#define rEE_SADDR (*(volatile u32 *)(EE_SADDR + 0x0000))
//CDK238 Specific register
//Ethernet Controller, CS8900A
#define rETHRxTx0 (*(volatile u16 *)(ETH_BADDR + ETH_IOBADDR + 0x0000))
#define rETHRxTx1 (*(volatile u16 *)(ETH_BADDR + ETH_IOBADDR + 0x0002))
#define rETHTxCMD (*(volatile u16 *)(ETH_BADDR + ETH_IOBADDR + 0x0004))
#define rETHTxLEN (*(volatile u16 *)(ETH_BADDR + ETH_IOBADDR + 0x0006))
#define rETHINTSTATQ (*(volatile u16 *)(ETH_BADDR + ETH_IOBADDR + 0x0008))
#define rETHPKTPGPTR (*(volatile u16 *)(ETH_BADDR + ETH_IOBADDR + 0x000a))
#define rETHPKTPGDATA0 (*(volatile u16 *)(ETH_BADDR + ETH_IOBADDR + 0x000c))
#define rETHPKTPGDATA1 (*(volatile u16 *)(ETH_BADDR + ETH_IOBADDR + 0x000e))
/*---------------------------------------------------------------------------------------------------------------
* Soft Vector Locations
---------------------------------------------------------------------------------------------------------------*/
//Exceptions
#define pISR_RESET (*(u32 *)(ISR_BADDR + 0x00))
#define pISR_UNDEF (*(u32 *)(ISR_BADDR + 0x04))
#define pISR_SWI (*(u32 *)(ISR_BADDR + 0x08))
#define pISR_PABORT (*(u32 *)(ISR_BADDR + 0x0c))
#define pISR_DABORT (*(u32 *)(ISR_BADDR + 0x10))
#define pISR_RESERVED (*(u32 *)(ISR_BADDR + 0x14))
#define pISR_IRQ (*(u32 *)(ISR_BADDR + 0x18))
#define pISR_FIQ (*(u32 *)(ISR_BADDR + 0x1c))
//HW interrupts
#define pISR_EXTFIQ (*(u32 *)(ISR_BADDR + 0x20))
#define pISR_BLINT (*(u32 *)(ISR_BADDR + 0x24))
#define pISR_WEINT (*(u32 *)(ISR_BADDR + 0x28))
#define pISR_MCINT (*(u32 *)(ISR_BADDR + 0x2c))
#define pISR_CSINT (*(u32 *)(ISR_BADDR + 0x30))
#define pISR_EINT1 (*(u32 *)(ISR_BADDR + 0x34))
#define pISR_EINT2 (*(u32 *)(ISR_BADDR + 0x38))
#define pISR_EINT3 (*(u32 *)(ISR_BADDR + 0x3c))
#define pISR_TC1OI (*(u32 *)(ISR_BADDR + 0x40))
#define pISR_TC2OI (*(u32 *)(ISR_BADDR + 0x44))
#define pISR_RTCMI (*(u32 *)(ISR_BADDR + 0x48))
#define pISR_TINT (*(u32 *)(ISR_BADDR + 0x4c))
#define pISR_UTXINT1 (*(u32 *)(ISR_BADDR + 0x50))
#define pISR_URXINT1 (*(u32 *)(ISR_BADDR + 0x54))
#define pISR_UMSINT (*(u32 *)(ISR_BADDR + 0x58))
#define pISR_SSEOTI (*(u32 *)(ISR_BADDR + 0x5c))
#define pISR_KBDINT (*(u32 *)(ISR_BADDR + 0x60))
#define pISR_SS2RX (*(u32 *)(ISR_BADDR + 0x64))
#define pISR_SS2TX (*(u32 *)(ISR_BADDR + 0x68))
#define pISR_UTXINT2 (*(u32 *)(ISR_BADDR + 0x6c))
#define pISR_URXINT2 (*(u32 *)(ISR_BADDR + 0x70))
#define pISR_DAIINT (*(u32 *)(ISR_BADDR + 0x74))
/*---------------------------------------------------------------------------------------------------------------
* Bit Definitions
---------------------------------------------------------------------------------------------------------------*/
//INTSR1/INTMR1
#define BIT_EXTFIQ (1<<0)
#define BIT_BLINT (1<<1)
#define BIT_WEINT (1<<2)
#define BIT_MCINT (1<<3)
#define BIT_CSINT (1<<4)
#define BIT_EINT1 (1<<5)
#define BIT_EINT2 (1<<6)
#define BIT_EINT3 (1<<7)
#define BIT_TC1OI (1<<8)
#define BIT_TC2OI (1<<9)
#define BIT_RTCMI (1<<10)
#define BIT_TINT (1<<11)
#define BIT_UTXINT1 (1<<12)
#define BIT_URXINT1 (1<<13)
#define BIT_UMSINT (1<<14)
#define BIT_SSEOTI (1<<15)
//INTSR2/INTR2
#define BIT_KBDINT (1<<0)
#define BIT_SS2RX (1<<1)
#define BIT_SS2TX (1<<2)
#define BIT_UTXINT2 (1<<12)
#define BIT_URXINT2 (1<<13)
//INTSR3/INTMR3
#define BIT_DAIINT (1<<0)
/*---------------------------------------------------------------------------------------------------------------
* SYSCON1
---------------------------------------------------------------------------------------------------------------*/
#define BIT_TC1M (1<<4)
#define BIT_TC1S (1<<5)
#define BIT_TC2M (1<<6)
#define BIT_TC2S (1<<7)
#define BIT_UART1EN (1<<8)
#define BIT_BZTOG (1<<9)
#define BIT_BZMOD (1<<10)
#define BIT_DBGEN (1<<11)
#define BIT_LCDEN (1<<12)
#define BIT_CDENTX (1<<13)
#define BIT_CDENRX (1<<14)
#define BIT_SIREN (1<<15)
#define BIT_EXCKEN (1<<18)
#define BIT_WAKEDIS (1<<19)
#define BIT_TRTXM (1<<20)
/*---------------------------------------------------------------------------------------------------------------
* SYSCON2
---------------------------------------------------------------------------------------------------------------*/
#define BIT_UART2EN (1<<8)
/*---------------------------------------------------------------------------------------------------------------
* LCDCON
---------------------------------------------------------------------------------------------------------------*/
#define BIT_GSEN (1<<30)
#define BIT_GSMD (1<<31)
/*---------------------------------------------------------------------------------------------------------------
* ARM Modes
---------------------------------------------------------------------------------------------------------------*/
#define MODE_USER 0x10 // 用户模式(User)
#define MODE_FIQ 0x11 // 快速中断模式(FIQ)
#define MODE_IRQ 0x12 // 外部中断模式(IRQ)
#define MODE_SVC 0x13 // 管理模式(Supervisor)
#define MODE_ABORT 0x17 // 数据访问终止模式(Abort)
#define MODE_UNDEF 0x1b // 未定义指令中止模式(Undifined)
#define MODE_MASK 0x1f //
#define MODE_NOINT 0xc0 //
#ifdef __cplusplus
}
#endif
#endif
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