myloop.c

本源码是液晶的12232b-4的控制程序 包括 读写

//-----------------------------------------------------------------------------
/*
* Copyright (c) 2007,光电图像处理教研室
* All rights reserved.
* 
* 文件名称：mmyloop.c
* 文件标识：myloop.c
* 摘    要：loop task
*
* 开发环境：Keil c51 750,EZ-USB FX2 Tools
* 
* 当前版本：1.0
* 作    者：冯剑
* 完成日期：20070720 12:00
*
* 取代版本：
* 原 作 者：
* 完成日期：
*
* 修改记录：
*/
/*-----------------------------------------------------------------------------*/
#pragma NOIV               // Do not generate interrupt vectors
#include ".\cypress\fx2.h"
#include ".\cypress\fx2regs.h"
#include ".\cypress\fx2sdly.h"
#include ".\app\ok.h"
#define	uchar BYTE
#define uint WORD
/*-----------------------------------------------------------------------------*/
void lcdinit(void);
void LcdClear(void);
void DrawBmp(unsigned char layer,uchar width,unsigned char const *bmp);
void	delay1s(unsigned char i);
void	wait1(unsigned char i);


/*-----------------------------------------------------------------------------*/
void init_port(void);
void	lcdini(void);
void clrscr(void);
void Draw_word(uchar d_where,uint x_add,uchar layer,uchar width);
/*-----------------------------------------------------------------------------*/

void main(void)
{  
    //USBCS &= ~bmRENUM;	
	//SYNCDELAY;
   // Renumerate if necessary.  Do this by checking the renum bit.  If it
   // is already set, there is no need to renumerate.  The renum bit will
   // already be set if this firmware was loaded from an eeprom.
    //EZUSB_Discon(FALSE);   // renumerate
    //USBCS &=~bmDISCON;
   	SYNCDELAY;
   	CPUCS = 0x32;
	  // E600 0011 0010
	  // PORTCSTB=1     , Read/write to PORTC generate RD# and WR# strobes
	  // CLKSPD[0,1]=10 , 8051 clock:48MHz
	  // CLKINV=0       , Don't invert CLKOUT signal
	  // CLKOE=1        , Drive CLKOUT signal
	  // 8051RES=0      , Don't reset 8051
  	SYNCDELAY;
	//////////////CKCON=0x00;// Set stretch to 0
	 	//The follow to configure the registers needed in the task
    IFCONFIG = 0xC8;
	SYNCDELAY;
	  // E601 1110 1000
      // IFCLKSRC=1    , FIFOs executes on internal clk source
      // xMHz=1        , 48MHz internal clk rate
      // IFCLKOE=0     , //tri state//////////Drive IFCLK pin signal at 48MHz
      // IFCLKPOL=0    , Don't invert IFCLK pin signal from internal clk
      // ASYNC=1       , master samples asynchronous
      // GSTATE=0      , Don't drive GPIF states out on PORTE[2:0]
      // IFCFG[1:0]=00 , FX2 in I/O model

	OED |= 0x80;
	IOD7 = 0;
	SYNCDELAY;
	SYNCDELAY;
	IOD7 = 1;
 init_port();                                                                                                    
 lcdini(); //reset                                                   
 clrscr(); //clr          
 
                                              
 Draw_word(0,0,0,16); //
 Draw_word(1,16,0,16); //
 Draw_word(2,32,0,16); //
 Draw_word(3,48,0,16); //
 Draw_word(0,64,0,16); //
 Draw_word(1,80,0,16); //
 Draw_word(2,96,0,16); //

 DrawBmp(1,120,Bmp002); //
 clrscr(); //
 while(1)
 	{
	delay1s(3);
	clrscr(); //
	wait1(3);
	DrawBmp(0,122,Bmp03); //超前科技
	} 

}