📄 net_phy.h
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/*
*********************************************************************************************************
* uC/TCP-IP
* The Embedded TCP/IP Suite
*
* (c) Copyright 2003-2007; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
*
* uC/TCP-IP is provided in source form for FREE evaluation, for educational
* use or peaceful research. If you plan on using uC/TCP-IP in a commercial
* product you need to contact Micrium to properly license its use in your
* product. We provide ALL the source code for your convenience and to help
* you experience uC/TCP-IP. The fact that the source code is provided does
* NOT mean that you can use it without paying a licensing fee.
*
* Network Interface Card (NIC) port files provided, as is, for FREE and do
* NOT require any additional licensing or licensing fee.
*
* Knowledge of the source code may NOT be used to develop a similar product.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* NETWORK PHYSICAL LAYER
*
* Micrel KSZ8721BL
*
* Filename : net_phy.h
* Version : V1.90
* Programmer(s) : EHS
*********************************************************************************************************
* Note(s) : (1) Supports Micrel KSZ8721BL PHY.
*
* (2) The MII interface port is assumed to be part of the host EMAC; consequently,
* reads from and writes to the PHY are made through the EMAC. The functions
* NetNIC_PhyRegRd() and NetNIC_PhyRegWr(), which are used to access the PHY, should
* be provided in the EMAC driver.
*********************************************************************************************************
*/
#ifndef _NET_PHY_H
#define _NET_PHY_H
/*
*********************************************************************************************************
* DEFINES
*********************************************************************************************************
*/
#define KSZ8721_INIT_AUTO_NEG_RETRIES 3 /* Attempt Auto-Negotiation 3 times */
#define KSZ8721_INIT_RESET_RETRIES 16 /* Check for successful reset 8 times */
#define KSZ8721_OUI 0x000885
#define KSZ8721_VNDR_MDL 0x21
/*
*********************************************************************************************************
* DP83848 REGISTER DEFINES
*********************************************************************************************************
*/
/* ------- Generic MII registers ---------- */
#define MII_BMCR 0x00 /* Basic mode control register */
#define MII_BMSR 0x01 /* Basic mode status register */
#define MII_PHYSID1 0x02 /* PHYS ID 1 */
#define MII_PHYSID2 0x03 /* PHYS ID 2 */
#define MII_ANAR 0x04 /* Advertisement control reg */
#define MII_ANLPAR 0x05 /* Link partner ability reg */
#define MII_ANER 0x06 /* Expansion register */
#define MII_ANNPTR 0x07 /* Next page transmit register */
#define MII_LPNPA 0x08 /* Link partner next page ability */
/* --------- Extended registers ----------- */
#define KSZ8721_RXER 0x15 /* RXER Counter */
#define KSZ8721_ISCSR 0x1B /* Interrupt Control/Status Register */
#define KSZ8721_PHYCTRL 0x1F /* 100BASE-TX PHY Controller */
/*
*********************************************************************************************************
* DP83848 REGISTER BITS
*********************************************************************************************************
*/
/* -------- MII_BMCR Register Bits -------- */
#define BMCR_RESV 0x007F /* Unused... */
#define BMCR_CTST DEF_BIT_07 /* Collision test */
#define BMCR_FULLDPLX DEF_BIT_08 /* Full duplex */
#define BMCR_ANRESTART DEF_BIT_09 /* Auto negotiation restart */
#define BMCR_ISOLATE DEF_BIT_10 /* Disconnect DP83840 from MII */
#define BMCR_PDOWN DEF_BIT_11 /* Powerdown the DP83840 */
#define BMCR_ANENABLE DEF_BIT_12 /* Enable auto negotiation */
#define BMCR_SPEED100 DEF_BIT_13 /* Select 100Mbps */
#define BMCR_LOOPBACK DEF_BIT_14 /* TXD loopback bits */
#define BMCR_RESET DEF_BIT_15 /* Reset the DP83840 */
/* -------- MII_BMSR Register Bits -------- */
#define BMSR_ERCAP DEF_BIT_00 /* Ext-reg capability */
#define BMSR_JCD DEF_BIT_01 /* Jabber detected */
#define BMSR_LSTATUS DEF_BIT_02 /* Link status */
#define BMSR_ANEGCAPABLE DEF_BIT_03 /* Able to do auto-negotiation */
#define BMSR_RFAULT DEF_BIT_04 /* Remote fault detected */
#define BMSR_ANEGCOMPLETE DEF_BIT_05 /* Auto-negotiation complete */
#define BMSR_RESV 0x07C0 /* Unused... */
#define BMSR_10HALF DEF_BIT_11 /* Can do 10mbps, half-duplex */
#define BMSR_10FULL DEF_BIT_12 /* Can do 10mbps, full-duplex */
#define BMSR_100HALF DEF_BIT_13 /* Can do 100mbps, half-duplex */
#define BMSR_100FULL DEF_BIT_14 /* Can do 100mbps, full-duplex */
#define BMSR_100BASE4 DEF_BIT_15 /* Can do 100mbps, 4k packets */
/* -------- MII_ANAR Register Bits -------- */
#define ANAR_SLCT 0x001F /* Selector bits */
#define ANAR_CSMA DEF_BIT_04 /* Only selector supported */
#define ANAR_10HALF DEF_BIT_05 /* Try for 10mbps half-duplex */
#define ANAR_10FULL DEF_BIT_06 /* Try for 10mbps full-duplex */
#define ANAR_100HALF DEF_BIT_07 /* Try for 100mbps half-duplex */
#define ANAR_100FULL DEF_BIT_08 /* Try for 100mbps full-duplex */
#define ANAR_100BASE4 DEF_BIT_09 /* Try for 100mbps 4k packets */
#define ANAR_RESV 0x1C00 /* Unused... */
#define ANAR_RFAULT DEF_BIT_13 /* Say we can detect faults */
#define ANAR_LPACK DEF_BIT_14 /* Ack link partners response */
#define ANAR_NPAGE DEF_BIT_15 /* Next page bit */
#define ANAR_FULL (ANAR_100FULL | ANAR_10FULL | ANAR_CSMA)
#define ANAR_ALL (ANAR_100FULL | ANAR_10FULL | ANAR_100HALF | ANAR_10HALF)
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