📄 bd_mst.h
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/******************************************************************************
Copyright (c) 2003 MStar Semiconductor, Inc.
All rights reserved.
[Module Name]: board.h
[Date]: 03-Dec-2003
[Comment]:
MST I/O control header file.
[Reversion History]:
*******************************************************************************/
#ifndef _MSBOARD_H_
#define _MSBOARD_H_
// system
#include "define.h"
#include "mcu.h"
////////////////////////////////////////////////
// Optional function
/////////////////////////////////////////////////
#define LANGUAGE_TYPE_SEL LANGUAGE_FOR_CHINA
#define ENABLE_PARENTCTL 1 // 20060316, Enable China parent control
/////////////////////////////////////////tecon
#define ENABLE_NO_SAVE 1 // 20060323, Enable No save for hotel.
#define LANGUAGE_FOR_US 0
#define LANGUAGE_FOR_CHINA 1
#define TV_NTSC 0
#define TV_PAL 1
#define TV_CHINA 2
#define TVP5147_PATCH 1
//#define DVDENABLE
#define Use_USB 0 // 20060325, 1-have USB, 0-no USB
#define Use_HDMI 1 // 20060325, 1-have HDMI, 0-no HDMI
#define IR_NEC_TL10S 0 // 20060403, define if use remote controller CR-TL10S.
// 1 - Haier remote controller CR-TL10S
// 0 - Haier remote controller HYF-35G
#if (IR_NEC_TL10S)
#define IR_TYPE IR_NEC
#else
#define IR_TYPE IR_TOSHIBA
#endif
#define VERSION_DEBUG 1 // //When Mass product, Must set 0 !!!
//#define PANEL_TYPE_SEL PNL_AU32_WXGA
#define PANEL_TYPE_SEL PNL_LG37_WXGA
//#define PANEL_TYPE_SEL PNL_SVA26_WXGA
//#define PANEL_TYPE_SEL PNL_FU17_FLC43_WXGA
//#define PANEL_TYPE_SEL PNL_AU37_WUXGA //1080P Panel, need #define MST5251_USE_DDRAM
//#define PANEL_TYPE_SEL PNL_SAMSUNG32_W2_WXGA
//#define PANEL_TYPE_SEL PNL_SAMSUNG40_WS_WXGA
//#define PANEL_TYPE_SEL PNL_CMO27B1_WXGA
#define OneAv 1
#define TwoAv 2
#define SAMPLE TwoAv
#define INITIAL 1
#define DEMO_001 2
#define KEYPAD INITIAL
#define DVI_CONNECT 0
#define HDMI_CONNECT 1
#define DIGITAL_CONNECT HDMI_CONNECT
#define SOUND_DVD 0
#define SOUND_SVIDEO 1
#define SOUND_LINEOUT SOUND_SVIDEO
#define ADC_AUTO_OFFSET 1
#define ENABLE_ATSC_SOURCE 0 // 20060124, When define Enable ATSC Module
#define ENABLE_HDMI_SOURCE 1 // 20060315, When need DVI HDMI source, set it.
#if (ENABLE_HDMI_SOURCE)
#define ENABLE_HDMI 1
#define ENABLE_HDCP 1
#else
#define ENABLE_HDMI 0
#define ENABLE_HDCP 0
#endif
#define AUDIO_I2S_DELAY 0 // Audio I2S input port (MSP34xx I2S out->MST5151A for Lip Sync)
#define DEBUG_HDMI_INF 0
// If ram size is small, don't enable 9 win
#define ENABLE_MULTI_WIN 0 // 1 => Enable 9 Win, 0 ==> Disable 9 Win77
#define ENABLE_MWE 0
#define ENABLE_POWER_SAVING 0
#define TV_SYSTEM TV_CHINA
#define VBI_FUNC_SEL SW_PARSER
//#define HDMI_480P_OVERSACAN //20060120, Enable HDMI 480i over scan function for test
#define SOUTH_AMERICA //20060209, When code for South American(Include PAL M, PAL N)
//#define MST5251_USE_DDRAM //20060220, When 5251+DDR Memory+1080P panel
////////////////////////////////////////////////////////
// Frame buffer setting
////////////////////////////////////////////////////////
// For PC&YPbPr use
//#define MAIN_FRAME_BFF_SEL MAIN_FRAME_BUFFER
#define MAIN_FRAME_BFF_SEL MAIN_FRAME_PC444
//#define MAIN_FRAME_BFF_SEL MAIN_FRAME_UXGA
/////////////////////////////////////////
// Main board definition
/////////////////////////////////////////
#define BD_90623_DEMO 0 // SDRAMx1 + Philips SAA7115 (default:MST90623)
#define BD_SOCKET_256 1 // SDRAM or DDRDRAM + Philips SAA7118
#define BD_SOCKET_208 2 // SDRAM or DDRDRAM + Philips SAA7118
#define BD_PABLO_TYPE_B 10 // SDRAM or DDRDRAM + Philips SAA7118 (default:MST5151)
#define BD_PABLO_DEMO 11 // DDRDRAMx2 + Micronas VPC3230 (default:MST5151)
#define BD_MST_09 12 // SDRAMx2 + TI TVP5146 (default:MST51512)
#define BD_MST_0B 13 // DDRDRAMx1(BGA) + Micronas VPC3230 (default:MST6251)
#define BD_MST_0B_NEW 14 // DDRDRAMx1(BGA) + Micronas VPC3230 (default:MST6251)
#define BD_SHENZHEN_DEMO 16
#define BD_UNKNOWN 0xFF
//#define DDR_NIBBLE_ACCESS
/////////////////////////////////////////
// Main board definition
/////////////////////////////////////////
#define BOARD_TYPE_SEL BD_SHENZHEN_DEMO
//TECON
//#define CHINA_DEMO_SET // For China demo set
///////////////////////////////////////////////////////////
// Board predefine setting
///////////////////////////////////////////////////////////
// 6151 + TVP5147
#if ( BOARD_TYPE_SEL == BD_SHENZHEN_DEMO )
#define BUS_TYPE_SEL DDR_NIBBLE_BUS
#define COMBFILTER_CHIP NOCOMB_CHIP
#define VIDEO_DECODER_SELECT VIDEO_DECODER_TVP51XX
#define VD_OUPUT_FORMAT VD_OUPUT_8BITS_ITU656
#define AUDIO_DECODE_SELECT AUDIO_DECODER_MSP34XX //AUDIO_DECODER_LV1116
#define TV_IF_AMPLIFIER TV_IF_AMPLIFIER_NONE
#ifdef MST5251_USE_DDRAM
#define RAM_TYPE DDR_8Mx16_2
#else
#define RAM_TYPE SDR_2Mx32_1
#endif
#define WIDE_PANEL 0
#define _4_3_PANEL 1
#define OTHER_PANEL 2
#define Type_9211 0
#define Type_6151 1
//#define Type_Select Type_6151
#define Type_Select Type_9211
#define BACKLIGHT_REG BK0_C3
#define DVIPLUG_REG BK0_C5
#define RM_EEPROM_TYPE RM_TYPE_24C16
//#define RM_EEPROM_TYPE RM_TYPE_24C32
#define NDBUS_ALE_IS_ON_P0 0 // 1: ALE is at uc P0
//////*********PNL_LG37_WXGA********************/
#define PANEL_HEIGHT 768
#define PANEL_TYPE WIDE_PANEL
//#define PANEL_TYPE _4_3_PANEL
//#define PANEL_TYPE OTHER_PANEL
/*
#define BOARDCHECKSUM 0xD8D8
#define BOARDCHECKSUMH BOARDCHECKSUM/0x100
#define BOARDCHECKSUML BOARDCHECKSUM%0x100*/
#endif
/////////////////////////////////////////
// MCU clock definition
/////////////////////////////////////////
// MCU external clock(crystal in)
//#define MCU_XTAL_CLK_HZ 24000000 // Hz
//#define MCU_XTAL_CLK_HZ 24576000 // Hz
//#define MCU_XTAL_CLK_HZ 22118000 // Hz
#define MCU_XTAL_CLK_HZ 22118400 // Hz
//#define MCU_XTAL_CLK_HZ 11059000 // Hz
#define MCU_XTAL_CLK_KHZ (MCU_XTAL_CLK_HZ / 1000)
#define MCU_XTAL_CLK_MHZ (MCU_XTAL_CLK_KHZ / 1000)
///////////////////////////////////////
// MCU delay definition
///////////////////////////////////////
#ifdef MCU_W77E532
#define MCU_MACHINE_CYCLE 4 // unit: oscillatory cycle
#else
#define MCU_MACHINE_CYCLE 12 // unit: oscillatory cycle
#endif
/////////////////////////////////////////////
// I2C pin definition
/////////////////////////////////////////////
#if ENABLE_HDCP
#define pinHDCP_HPD_RESET 0x40
#endif //ENABLE_HDCP
// MST I/O control definition
/////////////////////////////////////
#if (BOARD_TYPE_SEL==BD_SHENZHEN_DEMO)
//MCU_MTV412MV128
//MCU common I2C master
//===========================================================
#define i2cSCL_PIN P7_7
#define i2cSDA_PIN P3_4
#define i2cSCL_PIN_STATUS (P7_7 & _BIT0)
#define i2cSDA_PIN_STATUS _bit4_(P3)
#define i2cSCL_PIN_IN() {\
g_PadMod7 &=~0x80;\
PADMOD7 = g_PadMod7;\
}
#define i2cSCL_PIN_OUT() {\
g_PadMod7 |= 0x80;\
PADMOD7 = g_PadMod7;\
}
//MCU NV-Ram I2C master
//===========================================================
#define i2cSCLRam_PIN P7_5
#define i2cSDARam_PIN P7_6
#define i2cSCLRam_PIN_STATUS (P7_5 & _BIT0)
#define i2cSDARam_PIN_STATUS (P7_6 & _BIT0)
#define i2cSDARam_PIN_IN() {\
g_PadMod7 &=~0x40;\
PADMOD7 = g_PadMod7;\
}
#define i2cSDARam_PIN_OUT() {\
g_PadMod7 |= 0x40;\
PADMOD7 = g_PadMod7;\
}
#define i2cSCLRam_PIN_IN() {\
g_PadMod7 &= ~0x20;\
PADMOD7 = g_PadMod7;\
}
#define i2cSCLRam_PIN_OUT() {\
g_PadMod7 |= 0x20;\
PADMOD7 = g_PadMod7;\
}
//Led and keypad scan IO
//===========================================================
#define LED_POWER P6_0
#define LED_READING P6_1
#define LED_WRITING P1_7
#define LED_OK P1_6
#define SetLed_POWER() LED_POWER=1
#define ClrLed_POWER() LED_POWER=0
#define SetLed_READING() LED_READING=1
#define ClrLed_READING() LED_READING=0
#define SetLed_WRITING() LED_WRITING=1
#define ClrLed_WRITING() LED_WRITING=0
#define SetLed_OK() LED_OK=1
#define ClrLed_OK() LED_OK=0
#define pinReset_Plug (P5_0&_BIT0)
#define pinRead_Plug (P5_1&_BIT0)
#define pinWrite_Plug (P5_2&_BIT0)
#endif // end of #if (BOARD_TYPE_SEL==BD_SHENZHEN_DEMO)
#endif
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