📄 mcu.h
字号:
/******************************************************************************
Copyright (c) 2003 MStar Semiconductor, Inc.
All rights reserved.
[Module Name]: Mcu.h
[Date]: 04-Nov-2003
[Comment]:
MCU register definition.
[Reversion History]:
*******************************************************************************/
#ifndef _MCU_H_
#define _MCU_H_
// System
#include <reg52.h> // for the intended 8052 derivative
#include <intrins.h>
/////////////////////////////////////////
// MCU pin definition
/////////////////////////////////////////
sbit P0_0 = P0 ^ 0;
sbit P0_1 = P0 ^ 1;
sbit P0_2 = P0 ^ 2;
sbit P0_3 = P0 ^ 3;
sbit P0_4 = P0 ^ 4;
sbit P0_5 = P0 ^ 5;
sbit P0_6 = P0 ^ 6;
sbit P0_7 = P0 ^ 7;
sbit P1_0 = P1 ^ 0;
sbit P1_1 = P1 ^ 1;
sbit P1_2 = P1 ^ 2;
sbit P1_3 = P1 ^ 3;
sbit P1_4 = P1 ^ 4;
sbit P1_5 = P1 ^ 5;
sbit P1_6 = P1 ^ 6;
sbit P1_7 = P1 ^ 7;
sbit P2_0 = P2 ^ 0;
sbit P2_1 = P2 ^ 1;
sbit P2_2 = P2 ^ 2;
sbit P2_3 = P2 ^ 3;
sbit P2_4 = P2 ^ 4;
sbit P2_5 = P2 ^ 5;
sbit P2_6 = P2 ^ 6;
sbit P2_7 = P2 ^ 7;
sbit P3_0 = P3 ^ 0;
sbit P3_1 = P3 ^ 1;
sbit P3_2 = P3 ^ 2;
sbit P3_3 = P3 ^ 3;
sbit P3_4 = P3 ^ 4;
sbit P3_5 = P3 ^ 5;
sbit P3_6 = P3 ^ 6;
sbit P3_7 = P3 ^ 7;
/////////////////////////////////////////////////////////////////////
// PORT 4
// Another bit-addressable port P4 is also and only 4 bits(P4[3:0])
// can be used. This port address is located at D8 with the same
// function as that of port P1.
/////////////////////////////////////////////////////////////////////
#ifndef MCU_MTV412M
#ifdef MCU_W77E532
sfr P4 = 0xA5;
#else
sfr P4 = 0xD8;
sbit P4_0 = P4 ^ 0;
sbit P4_1 = P4 ^ 1;
sbit P4_2 = P4 ^ 2;
sbit P4_3 = P4 ^ 3;
#endif
#endif
////////////////////////////////////////////////////////////////
// #W78E516/62/65 MPU register
//
// Special Function Registers
////////////////////////////////////////////////////////////////
#ifndef MCU_MTV412M
sfr CHPCON = 0xBF; // In-System Programming Control Register
// b7: Software reset
// b6: Reserved
// b5: Reserved
// b4: Enable on-chip AUX-RAM
// b3: must set to 0
// b2: must set to 0
// b1: The Program Location Select(0:64K, 1:4K)
// b0: FLASH EPROM Programming Enable
sfr CHPENR = 0xF6; // #W78EXX MPU register
sfr SFRAL = 0xC4; // The objective address of on-chip FLASH EPROM in the in-system programming(low)
sfr SFRAH = 0xC5; // The objective address of on-chip FLASH EPROM in the in-system programming(high)
sfr SFRFD = 0xC6; // The programming data for on-chip FLASH EPROM in programming mode
sfr SFRCN = 0xC7; // The control byte of on-chip FLASH EPROM programming mode
// b7: Reserved
// b6: On-chip FLASH EPROM bank select for in-system programming(0: 64K, 1: 4K)
// b5: FLASH EPROM output enable
// b4: FLASH EPROM chip enable
// b3-0: The flash control signals
#endif
////////////////////////////////////////////////////////////////
// #W77E532 MPU register
//
// Special Function Registers
////////////////////////////////////////////////////////////////
#ifndef MCU_MTV412M
sfr ROMCON = 0xAB; // ROM banking Control Register
// b3: Enable on-chip ROM banking
// b2~b0: Select P1.x as A16
sfr PMR = 0xC4; // Power management Register
// b0: Enable on-chip AUX-RAM
sfr CKCON = 0x8E; // Clock control
// b2-0: movx duration
sfr TURBO_CHPCON = 0x9F; // ISP control register
sfr TA = 0xC7; // Times Access
#endif
////////////////////////////////////////////////////////////////
// #MTV412 MPU register
//
// Special Function Registers
////////////////////////////////////////////////////////////////
#ifdef MCU_MTV412M
#define XFR_ADDR 0xF00
#define XFR_DDC 0xE00
#define XFR_AUXRAM 0x800
#define AUXRAM (((unsigned char xdata*)XFR_AUXRAM)[0x00])
#define DDCRAM (((unsigned char xdata*)XFR_DDC)[0x00])
#define IICCTR (((unsigned char xdata*)XFR_ADDR)[0x00])
#define IICSTUSL (((unsigned char xdata*)XFR_ADDR)[0x01])
#define IICSTUSH (((unsigned char xdata*)XFR_ADDR)[0x02])
#define INTFLG (((unsigned char xdata*)XFR_ADDR)[0x03])
#define INTEN (((unsigned char xdata*)XFR_ADDR)[0x04])
#define MBUF (((unsigned char xdata*)XFR_ADDR)[0x05])
#define RCATXABUF (((unsigned char xdata*)XFR_ADDR)[0x06])
#define DDCCTR (((unsigned char xdata*)XFR_ADDR)[0x06])
#define SLVAADDR (((unsigned char xdata*)XFR_ADDR)[0x07])
#define SLVAADR (((unsigned char xdata*)XFR_ADDR)[0x07])
#define RCBTXBBUF (((unsigned char xdata*)XFR_ADDR)[0x08])
#define SLVBADDR (((unsigned char xdata*)XFR_ADDR)[0x09])
#define DBUF (((unsigned char xdata*)XFR_ADDR)[0x0A])
#define ISPSLV (((unsigned char xdata*)XFR_ADDR)[0x0B])
#define ISPEN (((unsigned char xdata*)XFR_ADDR)[0x0C])
#define WDT (((unsigned char xdata*)XFR_ADDR)[0x18])
#define DA0 (((unsigned char xdata*)XFR_ADDR)[0x20])
#define DA1 (((unsigned char xdata*)XFR_ADDR)[0x21])
#define DA2 (((unsigned char xdata*)XFR_ADDR)[0x22])
#define DA3 (((unsigned char xdata*)XFR_ADDR)[0x23])
#define DA4 (((unsigned char xdata*)XFR_ADDR)[0x24])
#define DA5 (((unsigned char xdata*)XFR_ADDR)[0x25])
#define DA6 (((unsigned char xdata*)XFR_ADDR)[0x26])
#define DA7 (((unsigned char xdata*)XFR_ADDR)[0x27])
#define DA8 (((unsigned char xdata*)XFR_ADDR)[0x28])
#define DA9 (((unsigned char xdata*)XFR_ADDR)[0x29])
#define DA10 (((unsigned char xdata*)XFR_ADDR)[0x2A])
#define DA11 (((unsigned char xdata*)XFR_ADDR)[0x2B])
#define DA12 (((unsigned char xdata*)XFR_ADDR)[0x2C])
#define DA13 (((unsigned char xdata*)XFR_ADDR)[0x2D])
#define INTEN1 (((unsigned char xdata*)XFR_ADDR)[0x49])
#define PADMOD0 (((unsigned char xdata*)XFR_ADDR)[0x50])
#define PADMOD1 (((unsigned char xdata*)XFR_ADDR)[0x51])
#define PADMOD2 (((unsigned char xdata*)XFR_ADDR)[0x52])
#define PADMOD3 (((unsigned char xdata*)XFR_ADDR)[0x53])
#define PADMOD4 (((unsigned char xdata*)XFR_ADDR)[0x54])
#define PADMOD5 (((unsigned char xdata*)XFR_ADDR)[0x55])
#define OPTION (((unsigned char xdata*)XFR_ADDR)[0x56])
#define PADMOD6 (((unsigned char xdata*)XFR_ADDR)[0x5E])
#define PADMOD7 (((unsigned char xdata*)XFR_ADDR)[0x5F])
#define XBANK (((unsigned char xdata*)XFR_ADDR)[0x35])
#define P4_0 (((unsigned char xdata*)XFR_ADDR)[0x58])
#define P4_1 (((unsigned char xdata*)XFR_ADDR)[0x59])
#define P4_2 (((unsigned char xdata*)XFR_ADDR)[0x5A])
#define P5_0 (((unsigned char xdata*)XFR_ADDR)[0x30])
#define P5_1 (((unsigned char xdata*)XFR_ADDR)[0x31])
#define P5_2 (((unsigned char xdata*)XFR_ADDR)[0x32])
#define P5_3 (((unsigned char xdata*)XFR_ADDR)[0x33])
#define P5_4 (((unsigned char xdata*)XFR_ADDR)[0x34])
#define P5_5 (((unsigned char xdata*)XFR_ADDR)[0x35])
#define P5_6 (((unsigned char xdata*)XFR_ADDR)[0x36])
#define P6_0 (((unsigned char xdata*)XFR_ADDR)[0x38])
#define P6_1 (((unsigned char xdata*)XFR_ADDR)[0x39])
#define P6_2 (((unsigned char xdata*)XFR_ADDR)[0x3A])
#define P6_3 (((unsigned char xdata*)XFR_ADDR)[0x3B])
#define P6_4 (((unsigned char xdata*)XFR_ADDR)[0x3C])
#define P6_5 (((unsigned char xdata*)XFR_ADDR)[0x3D])
#define P6_6 (((unsigned char xdata*)XFR_ADDR)[0x3E])
#define P6_7 (((unsigned char xdata*)XFR_ADDR)[0x3F])
#define P7_0 (((unsigned char xdata*)XFR_ADDR)[0x70])
#define P7_1 (((unsigned char xdata*)XFR_ADDR)[0x71])
#define P7_2 (((unsigned char xdata*)XFR_ADDR)[0x72])
#define P7_3 (((unsigned char xdata*)XFR_ADDR)[0x73])
#define P7_4 (((unsigned char xdata*)XFR_ADDR)[0x74])
#define P7_5 (((unsigned char xdata*)XFR_ADDR)[0x75])
#define P7_6 (((unsigned char xdata*)XFR_ADDR)[0x76])
#define P7_7 (((unsigned char xdata*)XFR_ADDR)[0x77])
#define HVSTUS (((unsigned char xdata*)XFR_ADDR)[0x40])//when read
#define HCNTH (((unsigned char xdata*)XFR_ADDR)[0x41])//when read
#define HCNTL (((unsigned char xdata*)XFR_ADDR)[0x42])//when read
#define VCNTH (((unsigned char xdata*)XFR_ADDR)[0x43])//when read
#define VCNTL (((unsigned char xdata*)XFR_ADDR)[0x44])//when read
#define HVCTR0 (((unsigned char xdata*)XFR_ADDR)[0x40])//when write
#define HVCTR2 (((unsigned char xdata*)XFR_ADDR)[0x42])//when write
#define HVCTR3 (((unsigned char xdata*)XFR_ADDR)[0x43])//when write
#define HVCTR4 (((unsigned char xdata*)XFR_ADDR)[0x44])//when write
#define HVINTFLG (((unsigned char xdata*)XFR_ADDR)[0x48])
#define HVINTEN (((unsigned char xdata*)XFR_ADDR)[0x49])
#define MADC (((unsigned char xdata*)XFR_ADDR)[0x10])
#define WDT (((unsigned char xdata*)XFR_ADDR)[0x18])
#endif // MCU_MTV412M
BOOL Enter_MTV412_ISP(void);
#endif
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -