adder.pt

来自「自动生成VERILOG 工具」· PT 代码 · 共 8 行

port theport vars rw0:data1, rw1:data2, r2:sum, r3:diff;

  input  [:]  data1, data2;
  output [:]  sum, diff;

  assign sum = data1 + data2;
  assign diff = data1 - data2;