perlilog.pm

自动生成VERILOG 工具

  $Perlilog::classes{$class} = 1;

  my ($file, $papa, $original) = @{$p};

  classload($papa, $schwonz); # Make sure parents are loaded

  # Now we create the package wrapping

  my $d = "package $class; use strict 'vars'; use Perlilog::PLerror;\n";
  $d.='@'.$class."::ISA=qw[$papa];\n";

  # Registering MUST be the last line before the text itself,
  # since the line number is recorded. Line count in error
  # messages begin immediately after the line that registers.

  $d.="&Perlilog::PLerror::register(\'$file\');\n# line 1 \"$file\"\n";

  open (CLASSFILE, $file) || 
    blow($schwonz."Failed to open resource file \'$file\' for class \'$class\'\n");
  $d.=join("",<CLASSFILE>);
  close CLASSFILE;
  eval($d);
  blow ($schwonz."Failed to load class \'$original\':\n $@")
    if ($@);
}

sub globalobj {
  return $Perlilog::globalobject if (ref $Perlilog::globalobject);
  puke("Global object was requested before init() was executed\n");
}

sub constreset {
  return globalobj()->constreset(@_);
}

sub execute {
  globalobj()->execute();
}

sub interface {
  puke("Attempt to call 'interface' from within an interface object (use intobjects instead)\n")
    if (defined $Perlilog::interface_rec);

  my $g=globalobj();

  puke("interface() called with non-object item\n")
    if (grep {not ($g->isobject($_))} @_);

  $Perlilog::interface_rec = globalobj->get('MAX_INTERFACE_REC');
  @Perlilog::interface_excuses=();

  my @obj=intobjects(@_);

  undef $Perlilog::interface_rec;

  if (@obj) {
    foreach (@obj) {
      $_->sustain();
    }
    return $obj[0];
  } else {
    my $p;
    my @names=();

    foreach $p (@_) {
      if ($g->isobject($p)) {
	push @names, $p->who();
      } else {
	push @names, "(Non-object item)";
      }
    }

    my $excuses = "";
    chomp @Perlilog::interface_excuses;
    foreach (@Perlilog::interface_excuses) {
      $excuses.="$_\n";
    }
    
    $excuses = "No adequate interface object found\n"
      unless (length($excuses));

    wrong("Failed to interface between ports:\n".
	  join("\n", @names)."\n----------\n$excuses");
    return undef;
  }
}

sub intobjects {
  puke("intobjects should be called only from within interface classes\n")
    unless (defined $Perlilog::interface_rec);
  if ($Perlilog::interface_rec<0) {
    fishy("Maximal interface object recursion (MAX_INTERFACE_REC) was reached. ".
	  "Are the interface objects registered in the wrong order, or is the design ".
	  "very complex?\n");
    return ();
} 
  my $c;
  my @obj;
  $Perlilog::interface_rec--;
  
  foreach $c (@Perlilog::interface_classes) {
    @obj = $c->attempt(@_);
    if (@obj) {
      if (globalobj()->isobject($obj[0])) {
	$obj[0]->set('perlilog-ports-to-connect', @_);
	last;
      }
      push @Perlilog::interface_excuses, "class $c: ".$obj[0]
	if (defined ($obj[0]) && $obj[0]=~/[a-z]/i);
      @obj=();
    }
  }
  $Perlilog::interface_rec++;
  return @obj;      
}

# This routine attempts to keep lines below 80 chrs/lines
sub linebreak {
  my $data = shift;
  my $extraindent = shift;

  $extraindent = '' unless (defined $extraindent);

  my @chunks = split("\n", $data);

  foreach (@chunks) {
    my $realout = '';
    while (1) { # Not forever. We'll break this in proper time
      if (/^.{0,79}$/) { # The rest fits well...
	$realout .= $_;
	last;
      }
      # We try to break the line after a comma.
      my ($x, $y) = (/^(.{50,78},)\s*(.*)$/);
      # Didn't work? A whitespace is enough, then.
      ($x, $y) = (/^(.{50,79})\s+(.*)$/)
	unless (defined $x);
      # Still didn't work? Break at first white space.
      ($x, $y) = (/^(.{50,}?)\s+(.*)$/)
	unless (defined $x);
      
      # THAT didn't work? Give up. Just dump it all out.
      unless (defined $x) {
	$realout .= $_;
	last;
      } else { # OK, we have a line split!
	$realout .= $x."\n";
	$_ = $extraindent.$y; # The rest, only indented.
      }
    }
    $_ = $realout;
  }
  my $final = join("\n", @chunks);
  $final .= "\n" if ($data =~ /\n$/);
  return $final;
}

# Just empty packages (used by PLroot).
package PL_hardroot;
package PL_settable;
package PL_const;

# And now the magic of autoloading.
package UNIVERSAL;
use Perlilog::PLerror;
$UNIVERSAL::errorcrawl='skip';
%UNIVERSAL::blacklist=();

sub AUTOLOAD {
  my $class = shift;
  my $method = $UNIVERSAL::AUTOLOAD;
  my ($junk,$file,$line)=caller;
  my $schwonz = "at $file line $line";
  return undef if $method =~ /::SUPER::/;

  my ($package) = $method =~ /^(.*?)::/;
  $method =~ s/.*:://;

  my $name = ref($class);

  return undef if ($method eq 'DESTROY');
  
  print "$class, $package\n"  unless ($class eq $package);
  puke("Undefined function/method \'$method\' $schwonz\n")
    unless ($class eq $package);

  if ($name) {
    # Forgive. This is not our class anyway...
    return undef;
  }

  # Now we protect ourselves against infinite recursion, should
  # the classload call fail silently. This will happen if the
  # first attempt to call a method in a class is to a
  # method that isn't defined.
  puke("Undefined method \'$method\' in class \'$class\' $schwonz\n")
    if $UNIVERSAL::blacklist{$class};
  $UNIVERSAL::blacklist{$class}=1;

  &Perlilog::classload($class,
		       "While trying to load class \'$class\' due to call ".
		       "of method \'$method\' $schwonz:\n");
 
  #Just loaded the new class? Let's use it!
  return $class->$method(@_);
}

# Now have the "defineclass" subroutine defined, so we can use it to
# generate bareword warnings for anything but a class name.



1; # Return true

__END__

=head1 NAME

Perlilog - Verilog environment and IP core handling in Perl

=head1 SYNOPSIS

  use Perlilog; 

=head1 DESCRIPTION

The project is extensively documented in Perlilog's user guide, which can be downloaded at the project's
home page, L<http://www.opencores.org/perlilog/>, or at my own:  L<http://www.billauer.co.il/perlilog.html>.

In wide terms, Perlilog is a Perl environment for Verilog code manipulation. It supplies the Perl programmer
with several strong tools for managing Perl modules and connecting between them.

Originally, Perlilog was intended for integration of Verilog IP cores, but it's useful for the following
tasks as well:

=over 4

=item *

Scripts that generate Verilog code automatically

=item *

"Hook-up" of modules: Assigning pins, connecting to ASIC pads, etc.

=item *

Automatic generation of buses and bus controllers, with a variable number of members and parametrized
arbitration rules

=item *

Automatic generation of bridges when needed to interface between different bus protocols

=back

=head1 ACKNOWLEDGEMENTS

This project would not exist without the warm support of Flextronics Semiconductors in Israel,
and Dan Gunders in particular.

=head1 AUTHOR

Eli Billauer, E<lt>[e-mail]<gt>

=head1 SEE ALSO

The Perlilog project's home page: L<http://www.opencores.org/perlilog/>

The author's home page: L<http://www.billauer.co.il/>

The Eobj project: L<http://www.billauer.co.il/eobj.html>

=cut