📄 hardware.lst
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00008B27 09 23 40 00 r1 -= 0x40;
00008B29 19 D3 17 70 [P_DAC1] = r1;
00008B2B 4A 4E jnz L_RD_Loop;
L_RD_End:
00008B2C 90 90 pop r1,r2 from [sp];
00008B2D 90 9A retf;
.ENDP
///////////////////////////////////////
_SP_RampUpDAC2: .PROC
F_SP_RampUpDAC2:
00008B2E 90 D4 push r1,r2 to [sp];
00008B2F 11 93 16 70 r1=[P_DAC2];
00008B31 09 B3 C0 FF r1 &= ~0x003f;
00008B33 09 43 00 80 cmp r1,0x8000
00008B35 0E 0E jb L_RU_NormalUp_;
00008B36 5D 5E je L_RU_End;
L_RU_DownLoop_:
00008B37 40 F0 64 8B call F_Delay;
00008B39 41 94 r2 = 0x0001;
00008B3A 1A D5 12 70 [P_Watchdog_Clear] = r2;
00008B3C 09 23 40 00 r1 -= 0x40;
00008B3E 19 D3 16 70 [P_DAC2] = r1;
00008B40 09 43 00 80 cmp r1,0x8000;
00008B42 4C 4E jne L_RU_DownLoop_;
L_RD_DownEnd_:
00008B43 0C EE jmp L_RU_End_;
L_RU_NormalUp_:
L_RU_Loop_:
00008B44 40 F0 64 8B call F_Delay;
00008B46 41 94 r2 = 0x0001;
00008B47 1A D5 12 70 [P_Watchdog_Clear] = r2;
00008B49 09 03 40 00 r1 += 0x40;
00008B4B 19 D3 16 70 [P_DAC2] = r1;
00008B4D 09 43 00 80 cmp r1, 0x8000;
00008B4F 4C 4E jne L_RU_Loop_;
L_RU_End_:
00008B50 90 90 pop r1,r2 from [sp];
00008B51 90 9A retf;
.ENDP
///////////////////////////////////////
_SP_RampDnDAC2: .PROC
F_SP_RampDnDAC2:
//int off;
00008B52 90 D4 push r1,r2 to [sp];
00008B53 11 93 16 70 r1 = [P_DAC2];
00008B55 09 B3 C0 FF r1 &= ~0x003F;
00008B57 0A 5E jz L_RD_End_;
L_RD_Loop_:
00008B58 40 F0 64 8B call F_Delay;
00008B5A 41 94 r2 = 0x0001;
00008B5B 1A D5 12 70 [P_Watchdog_Clear] = r2;
00008B5D 09 23 40 00 r1 -= 0x40;
00008B5F 19 D3 16 70 [P_DAC2] = r1;
00008B61 4A 4E jnz L_RD_Loop_;
L_RD_End_:
00008B62 90 90 pop r1,r2 from [sp];
00008B63 90 9A retf;
.ENDP
////////////////////////////////////////
F_Delay:
00008B64 88 D2 push r1 to [sp];
00008B65 48 92 r1 = 8;
L_D_Loop:
00008B66 41 22 r1 -= 1;
00008B67 42 4E jnz L_D_Loop;
00008B68 88 90 pop r1 from [sp];
00008B69 90 9A retf;
///////////////////////////////////////////
// Function: Initial Queue
// Destory: R1,R2
///////////////////////////////////////////
F_SP_InitQueue:
00008B6A 09 93 B3 01 R1 = R_Queue;
00008B6C 40 94 R2 = 0;
L_ClearQueueLoop:
00008B6D D1 D4 [R1++] = R2;
00008B6E 09 43 E5 01 cmp R1, R_Queue+C_QueueSize;
00008B70 44 4E jne L_ClearQueueLoop;
00008B71 40 92 R1 = 0;
00008B72 19 D3 E5 01 [R_ReadIndex] = R1;
00008B74 19 D3 E6 01 [R_WriteIndex] = R1;
00008B76 90 9A retf;
///////////////////////////////////////////
// Function: Get a data form Queue
// Output: R1: Data
// R2: return value
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue:
00008B77 12 95 E5 01 R2 = [R_ReadIndex];
00008B79 12 45 E6 01 cmp R2,[R_WriteIndex];
00008B7B 0C 5E je L_RQ_QueueEmpty;
00008B7C 0A 05 B3 01 R2 += R_Queue; // get queue data address
00008B7E C2 92 R1 = [R2];
00008B7F 12 95 E5 01 R2 = [R_ReadIndex];
00008B81 41 04 R2 += 1;
00008B82 72 44 cmp R2, C_QueueSize;
00008B83 01 4E jne L_RQ_NotQueueBottom;
00008B84 40 94 R2 = 0;
L_RQ_NotQueueBottom:
00008B85 1A D5 E5 01 [R_ReadIndex] = R2;
//r2 = 0x0000; // get queue data
00008B87 90 9A retf;
L_RQ_QueueEmpty:
//r2 = 0x8000; // queue empty
00008B88 90 9A retf;
///////////////////////////////////////////
// Function: Put a data to Queue
// R1: Input
// Destory: R1,R2,R3
///////////////////////////////////////////
F_SP_WriteQueue:
00008B89 12 95 E6 01 R2 = [R_WriteIndex]; // put data to queue
00008B8B 0A 05 B3 01 R2 += R_Queue;
00008B8D C2 D2 [R2] = R1;
00008B8E 12 95 E6 01 R2 = [R_WriteIndex];
00008B90 41 04 R2 += 1;
00008B91 72 44 cmp R2, C_QueueSize;
00008B92 01 4E jne L_WQ_NotQueueBottom;
00008B93 40 94 R2 = 0;
L_WQ_NotQueueBottom:
00008B94 1A D5 E6 01 [R_WriteIndex] = R2;
00008B96 90 9A retf;
//..........................................
F_SP_TestQueue:
//... Test Queue Empty ...
00008B97 11 93 E5 01 R1 = [R_ReadIndex];
00008B99 11 43 E6 01 cmp R1,[R_WriteIndex];
00008B9B 11 5E je L_TQ_QueueEmpty;
//... Test Queue Full ...
00008B9C 11 93 E5 01 R1 = [R_ReadIndex]; // For N Queue Full: 1. W=R-1 2.R=0/W=N-1
00008B9E 04 4E jnz L_TQ_JudgeCond2;
00008B9F 11 93 E6 01 R1 = [R_WriteIndex];
00008BA1 71 42 cmp R1, C_QueueSize-1; // Cond1
00008BA2 08 5E je L_TQ_QueueFull;
L_TQ_JudgeCond2:
00008BA3 11 93 E5 01 R1 = [R_ReadIndex];
00008BA5 41 22 R1 -=1;
00008BA6 11 43 E6 01 cmp R1,[R_WriteIndex];
00008BA8 02 5E je L_TQ_QueueFull;
00008BA9 40 92 r1 = 0; // not Full, not empty
00008BAA 90 9A retf;
L_TQ_QueueFull:
00008BAB 41 92 r1 = 1; // full
00008BAC 90 9A retf;
L_TQ_QueueEmpty:
00008BAD 42 92 r1 = 2; // empty
00008BAE 90 9A retf;
//.........................................
//////////////////////////////////////////////////////
// SACM_GetResource(Address,Page,offset);
//////////////////////////////////////////////////////
_SP_GetResource: .PROC
00008BAF 88 DA push bp to [sp];
00008BB0 08 0B 01 00 bp = sp + 1;
//push r2 to [sp];
00008BB2 03 92 r1 = [bp+3]; // address
00008BB3 04 94 r2 = [bp+4]; // bank
00008BB4 5A 95 r2 = r2 lsl 4;
00008BB5 5A 95 r2 = r2 lsl 4;
00008BB6 4A 95 r2 = r2 lsl 2;
00008BB7 7F BC sr &= 0x03f;
00008BB8 06 A5 r2 |=sr;
00008BB9 02 9D sr = r2;
00008BBA E1 92 r1 = D:[r1];
//pop r2 from [sp];
00008BBB 88 98 pop bp from [sp];
00008BBC 90 9A retf;
.ENDP
_SP_Delay: .PROC
F_SP_Delay:
00008BBD 90 9A retf;
.ENDP
//========================================================================================
// End of hardware.asm
//========================================================================================
0 error(s), 0 warning(s).
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