rominit.s

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/* romInit.s - Motorola 860ads ROM initialization module */



#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "regs.h"	
#include "sysLib.h"
#include "drv/multi/ppc860Siu.h"
	
	/* internals */

	.globl	_romInit	/* start of system code */
	.globl	romInit		/* start of system code */
	
	/* externals */

	.extern romStart	/* system initialization routine */

	.text
	.align 2

/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
SYPCR_1	.equ	0x0004
SWSR_1	.equ	0x000E

* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )

*/

_romInit:
romInit:
	bl	cold		/* jump to the cold boot initialization */
	
	bl	start		/* jump to the warm boot initialization */

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1984-1996 Wind River Systems, Inc."
	.ascii   "Copyright 1999-2000 ComLeader Inc., E1-R"
	.align 2

cold:
	li	r3, BOOT_COLD	/* set cold boot as start type    BOOT_COLD=0x02*/

	/*
	 * When the PowerPC 860 is powered on, the processor fletch the
	 * instructions located at the address 0x100. We need to jump
	 * from the address 0x100 to the Flash space.
	 */

	lis	r4, HIADJ(start)
	addi	r4, r4, LO(start)		/* of start */

	lis	r5, HIADJ(romInit)		/* load r5 with the address */
	addi	r5, r5, LO(romInit)		/* of romInit() */

	lis	r6, HIADJ(ROM_TEXT_ADRS)	/* load r6 with the address */
	addi	r6, r6, LO(ROM_TEXT_ADRS)	/* of ROM_TEXT_ADRS */

	sub	r4, r4, r5			/*  */
	add	r4, r4, r6 

	mtspr	LR, r4				/* save destination address*/
						/* into LR register */
	blr					/* jump to flash mem address */
			
start:
	/* set the MSR register to a known state */

	/*xor	r4, r4, r4*/		/* clear register R4 */
	/*mtmsr 	r4*/			/* cleat the MSR register */
       
        lis	r4, HIADJ(0x1002)
		addi	r4, r4, LO(0x1002)
        mtmsr 	r4
        xor	r4, r4, r4
       
	/* DER - clear the Debug Enable Register */

	mtspr	DER, r4

	/* ICR - clear the Interrupt Cause Register */

	mtspr	ICR, r4

	/* 
	 * ICTRL - initialize the Intstruction Support Control register
	 *	   
	 */

	lis	r5, HIADJ(0x00000007)
	addi	r5, r5, LO(0x00000007)
	mtspr	ICTRL, r5

	/* disable the instruction/data cache */
	
	lis	r4, HIADJ ( CACHE_CMD_DISABLE)		/* load disable cmd */
	addi	r4, r4, LO (CACHE_CMD_DISABLE)
	mtspr	IC_CST, r4				/* disable I cache */
	mtspr	DC_CST, r4				/* disable D cache */

	/* unlock the instruction/data cache */

	lis	r4, HIADJ ( CACHE_CMD_UNLOCK_ALL)	/* load unlock cmd */
	addi	r4, r4, LO (CACHE_CMD_UNLOCK_ALL)
	mtspr	IC_CST, r4			/* unlock all I cache lines */
	mtspr	DC_CST, r4			/* unlock all D cache lines */

	/* invalidate the instruction/data cache */

	lis	r4, HIADJ (CACHE_CMD_INVALIDATE)   /* load invalidate cmd*/
	addi	r4, r4, LO (CACHE_CMD_INVALIDATE)
	mtspr	IC_CST, r4		/* invalidate all I cache lines */
	mtspr	DC_CST, r4		/* invalidate all D cache lines */

	/*
	 * initialize the IMMR register before any non-core registers
	 * modification.
	 */

	lis	r4, HIADJ( INTERNAL_MEM_MAP_ADDR)	
	addi	r4, r4, LO(INTERNAL_MEM_MAP_ADDR)
	mtspr	IMMR, r4		/* initialize the IMMR register */

	mfspr	r4, IMMR		/* read it back, to be sure */
	rlwinm  r4, r4, 0, 0, 15	/* only high 16 bits count */

	/* SYPCR - turn off the system protection stuff */

#ifdef USE_NO_WATCHDOG
	lis	r5, HIADJ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
	addi	r5, r5, LO(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
	stw	r5, SYPCR(0)(r4)

	
	
/*
	lis r5, HIADJ(0x00004000)
	addi r5,r5,LO(0x00004000)
	
	stw r5,PLPRCR(0)(r4)
*/

#else	

	lis	r5, HIADJ( SYPCR_SWTC | SYPCR_BMT |  SYPCR_SWE | SYPCR_SWRI |SYPCR_SWP)
	addi	r5, r5, LO(SYPCR_SWTC | SYPCR_BMT | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
	stw	r5, SYPCR(0)(r4)

/*
	lis r5, HIADJ(0x00000000)
	addi r5,r5,LO(0x00000000)
	
	stw r5,PITR(0)(r4)
*/


	lis r5,HIADJ(0x55AACC33)
	addi r5,r5,LO(0x55AACC33)
	stw r5,PITCK(0)(r4)
	
	li	r5,0x0001
	sth r5,PISCR(0)(r4)

	
/*	
	lis r5, HIADJ(0xFFFFFFFF)
	addi r5,r5,LO(0xFFFFFFFF)
	
	stw r5,PITC(0)(r4)
*/
	li r5,0x556c
	sth r5,SWSR(0)(r4)

	li r5,0xAA39
	sth r5,SWSR(0)(r4)
	
#endif

	/*
	 * Map the bank 0 to the flash area - On the ADS board at reset time
	 * the bank 0 is already used to map the flash.
	 */

	lis	r5, HIADJ( 0x12800401)
	addi	r5, r5, LO(0x12800401)
	stw	r5, BR0(0)(r4)


	lis	r5, HIADJ( 0xfff80930)
	addi	r5, r5, LO(0xfff80930)
	stw	r5, OR0(0)(r4)
	
	/*
	 * Map the bank 1 to the Board Status and Control Registers
	 */
	lis	r5, HIADJ( 0x22800801)
	addi	r5, r5, LO(0x22800801)
	stw	r5, BR1(0)(r4)


	lis	r5, HIADJ( 0xffc00930)
	addi	r5, r5, LO(0xffc00930)
	stw	r5, OR1(0)(r4)
	
	/* Check for FADS,  set the SIUMCR accordingly */
	
	/* set the SIUMCR register for important debug port, etc... stuff */

	lis	r6, HIADJ( SIUMCR_FRC	       | SIUMCR_DLK  | SIUMCR_DPC | \
			   SIUMCR_MLRC_3STATES | SIUMCR_AEME | SIUMCR_GB5E)
	addi	r6, r6, LO(SIUMCR_FRC	       | SIUMCR_DLK  | SIUMCR_DPC | \
			   SIUMCR_MLRC_3STATES | SIUMCR_AEME | SIUMCR_GB5E)
	b	siu_done

	
siu_done:	

	lwz	r5, SIUMCR(0)(r4)
	or	r5, r5, r6
	stw	r5, SIUMCR(0)(r4)

	/* TBSCR - initialize the Time Base Status and Control register */

	lis	r5, HIADJ( TBSCR_REFA | TBSCR_REFB)
	addi	r5, r5, LO(TBSCR_REFA | TBSCR_REFB)
	sth	r5, TBSCR(0)(r4)

	/* set PIT status and control init value */

	li	r5, PISCR_PS | PISCR_PITF
	sth	r5, PISCR(0)(r4)

	/* set the SPLL frequency */

	lis	r5, HIADJ( 0x00904000)
	addi	r5, r5, LO(0x00904000)
	stw	r5, PLPRCR(0)(r4)

	/* 
	 * we program the MPTPR with the largest allowed divider 
	 * and the PTA value accordingly. So here we figure out the 
	 * correct value for the PTA field.
	 */

	/* try with the divider by 64 */

	li	r6, MPTPR_PTP_DIV64 
        sth	r6, MPTPR(0)(r4)
 
        /* 
	 * initialize MxMR but don't enable refresh until after 
	 * SDRAM initialization.
         */

        lis     r6, HIADJ (0x0c002111)
        addi    r6, r6, LO (0x0c002111)
    /*    or      r6, r6, r11    */                  
        stw     r6, MAMR(0)(r4)
  

upmbInit:
 
        /*
         * load r6/r7 with the start/end address of the UPM table for an
         * SDRAM @ 50MHZ.
         */

        lis     r6, HIADJ( upmbTableSdram)
        addi    r6, r6, LO(upmbTableSdram)
        lis     r7, HIADJ( upmbTableSdramEnd)
        addi    r7, r7, LO(upmbTableSdramEnd)
 
        /* init UPMA for memory access cr-z */
 
        sub     r5, r7, r6              /* compute table size */
        srawi   r5, r5, 2               /* in integer size */
 
        /* convert UpmTable to ROM based addressing */
 
        lis     r7, HIADJ(romInit)
        addi    r7, r7, LO(romInit)
 
        lis     r8, HIADJ(ROM_TEXT_ADRS)
        addi    r8, r8, LO(ROM_TEXT_ADRS)
 
        sub     r6, r6, r7              /* subtract romInit base address */
        add     r6, r6, r8              /* add in ROM_TEXT_ADRS address */
 
        lis     r9, HIADJ (0x6000)
        addi    r9, r9, LO(0x6000)
 
UpmbWriteLoop:
        /* write the UPM table in the UPM */
        

        lwz     r10, 0(r6)              /* get data from table */
        stw     r10, MDR(0)(r4)         /* store the data to MD register */
 
        stw     r9, MCR(0)(r4)          /* issue command to MCR register */
 
        addi    r6, r6, 4               /* next entry in the table */
        addi    r9, r9, 1               /* next MAD address */


        addi    r5,r5,-1
        cmpwi   r5,0
        bne     UpmbWriteLoop

/* write or2 br2 mamr the second time */

	/* program OR2 and BR2 for epld Memory Array */
/*
	li r5,0xAA39
	sth r5,SWSR(0)(r4)
*/
	lis	r5, HIADJ (0x13000001)
	addi    r5, r5, LO (0x13000001)
	stw	r5, BR2(0)(r4)
	
    lis	r5, HIADJ (0xffc00920)
	addi    r5, r5, LO (0xffc00920)
	stw	r5, OR2(0)(r4)

    /* program OR3 and BR3 for 4M Memory Array */


	lis	r5, HIADJ (0x00000081)
	addi    r5, r5, LO (0x00000081)
	stw	r5, BR3(0)(r4)

	lis	r5, HIADJ (0xff800e00)
	addi    r5, r5, LO (0xff800e00)
	stw	r5, OR3(0)(r4)
   

	/* enable SDRAM refresh cycles */

        lis     r5, HIADJ (0x0c802111)
        addi    r5, r5,LO (0x0c802111)
	/*add	r5, r5, r11*/
        stw     r5, MAMR(0)(r4)



        /* 
         * Issue precharge command (PRCG) and wait the precharge time (t-rp).
	 * Run precharge pattern from UPMB location 5.
         */

        lis     r5, HIADJ(0x80006105)	/*zjl: for cs3 08-15-00*/
        addi    r5, r5, LO(0x80006105)
        stw     r5, MCR(0)(r4)
        
   
 
        /* run refresh pattern 8 times */

        lis     r5, HIADJ(0x80006830)	/*zjl: for cs3 08-15-00*/
        addi    r5, r5, LO(0x80006830)
        stw     r5, MCR(0)(r4)
        
       
 
        /* 
	 * Configure the 32 bit address to be output on the address bus 
	 * if AMX = 0xb11.
         * See section 16.6.4.1 "Arm Words".  The following values must 
	 * be placed on the defined SDRAM address pins:
         *   A[9]   = 0          burst write mode
         *   A[6:4] = 010        cas latency of two
         *   A[3]   = 0          sequential mode
         *   A[2:0] = 010        burst length 4
         *
         * The address must be shifted left by 2 bits for 32 bit wide SDRAM...
         *   (0b0100010 << 2) = 0x88
         */

        lis     r5, HIADJ(0x02000088)
        addi    r5, r5, LO(0x02000088)
        stw     r5, MAR(0)(r4)
 
        /* 
	 * issue a mode register set (MRS) to initialize the SDRAM mode 
	 * register.  This programs the burst length, CAS latency and 
	 * write mode. Run MRS pattern from UPMB location 6.
         */

        lis     r5, HIADJ(0x80006106)	/*for cs3*/
        addi    r5, r5, LO(0x80006106)
        stw     r5, MCR(0)(r4)
        
       

	/* program OR2,3,4 and BR2,3,4 again  */


    	lis	r5, HIADJ (0xffc00920)
	addi    r5, r5, LO (0xffc00920)
	stw	r5, OR2(0)(r4)

	lis	r5, HIADJ (0x13000001)
	addi    r5, r5, LO (0x13000001)
	stw	r5, BR2(0)(r4)

	lis	r5, HIADJ (0xff000e00)
	addi    r5, r5, LO (0xff000e00)
	stw	r5, OR3(0)(r4)	
	
	
	lis	r5, HIADJ (0x00000081)
	addi    r5, r5, LO (0x00000081)
	stw	r5, BR3(0)(r4)
   
   

	/* enable SDRAM refresh cycles */

        lis     r5, HIADJ (0x0c802111)
        addi    r5, r5,LO (0x0c802111)
	/*add	r5, r5, r11*/
        stw     r5, MAMR(0)(r4)


 
        /* initialize the stack pointer */
	lis	sp, HIADJ(STACK_ADRS)
	addi	sp, sp, LO(STACK_ADRS)
	
        /* initialize r2 and r13 according to EABI standard */
#if	FALSE					/* SDA Not supported yet */

	lis	r2, HIADJ(_SDA2_BASE_)
	addi	r2, r2, LO(_SDA2_BASE_)

	lis	r13, HIADJ(_SDA_BASE_)
	addi	r13, r13, LO(_SDA_BASE_)
#endif

	/* go to C entry point */

	addi	sp, sp, -FRAMEBASESZ		/* get frame stack */

	/* 
	 * calculate C entry point: routine - entry point + ROM base 
	 * routine	= romStart
	 * entry point	= romInit	= R7
	 * ROM base	= ROM_TEXT_ADRS = R8
	 * C entry point: romStart - R7 + R8 
	 */
	 

        lis	r6, HIADJ(romStart)	
        addi	r6, r6, LO(romStart)	/* load R6 with C entry point */

	sub	r6, r6, r7		/* routine - entry point */
	add	r6, r6, r8 		/* + ROM base */

	mtlr	r6			/* move C entry point to LR */
	blr				/* jump to the C entry point */



/* This 50 MHz SDRAM table is for...
 *   860EN Rev B.1 9829 and newer silicon
 *   860T  Rev B.3 9832 and newer silicon
 *
 * This table will NOT work with older 860EN or 860T parts.
 */
 
upmbTableSdram:
 
/* single read   (offset 0x00 in upm ram) */
       .long   0x0f07fc04, 0xeeaefc04, 0x01adfc04, 0xefbbbc00
       .long   0x0ff77c40, 0x0ff77c35, 0xefeabc34, 0x0fb57c35
/* burst read    (offset 0x08 in upm ram) */
       .long   0x1f03fc04, 0xeeaefc04, 0x10acfc04, 0xf0affc00
       .long   0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff33c43
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* single write  (offset 0x18 in upm ram) */
       .long   0x0f07fc04, 0xeeaebc00, 0x01a93c00, 0x0ff77c47
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* burst write   (offset 0x20 in upm ram) */
       .long   0x1f03fc04, 0xeeaebc00, 0x10ac3c00, 0xf0affc00
       .long   0xf0affc00, 0xe1bbbc00, 0x1ff33c47, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* refresh       (offset 0x30 in upm ram) */
       .long   0x0ff0fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04
       .long   0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* exception     (offset 0x3C in upm ram) */
       .long   0x7ffffc07, 0xfffffc04, 0xfffffc04, 0xfffffc04
 
upmbTableSdramEnd: