📄 cnmtesta.vhd
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IBSCI: IBUF port map (I=>SCI_CLK, O=>iSCI_CLK);
OBMCU: OBUF port map (I=>iSCI_CLK, O=>MCU_P35);
--BEGIN calibration control
-- this will measure off approx. 10 seconds then toggle AD_CAL to allow
-- ADC to warm up after power up before initiating a calibration cycle
process (iOSC_CLOCK, iADCAL_OFF)
begin
if iOSC_CLOCK'event and iOSC_CLOCK = '1' then
if iADCAL_OFF = '0' then
iADCAL_CNT <= iADCAL_CNT + 1;
end if;
end if;
end process;
iADCAL_ON <= '1' when iADCAL_CNT = "10011111" else '0';
--this flip-flop will latch a signal after a certain period of time (~10 sec)
--and this signal is used to stop the calibration cycle. Happens only once
--after a reset or power up.
process (iOSC_CLOCK, iADCAL_ON)
begin
if iOSC_CLOCK'event and iOSC_CLOCK = '1' then
if iADCAL_ON = '1' then
iADCAL_OFF <= '1';
end if;
end if;
end process;
FDADC0: FDCE port map (D=>iADCAL_ON, CE=>logic_one, CLR=>logic_zero, C=>iOSC_CLOCK, Q=>ifADCAL_ON);
--do manual calibration (by MCU that is) with this flip-flop
FDADC1: FDCE port map (D=>iData_in(0), CE=>iADC_CAL_SEL, CLR=>logic_zero, C=>iWRn_clk, Q=>iuADC_CAL);
iADC_CAL <= iuADC_CAL or ifADCAL_ON;
OBFADCAL: OBUF port map (I=>iADC_CAL, O=>AD_CAL);
iADC_CAL_RD <= not (iADC_CAL_SEL and not iRDn);
BTADCAL: BUFT port map (I=>iADCAL_OFF, T=>iADC_CAL_RD, O=>iData_out(0));
--END of calibration control
--set DAC Modes and DAC reset
OFDDAC0: OFDX port map (D=>iData_in(0), CE=>iDACMODE_SEL, C=>iWRn_clk, Q=>DACM2);
OFDDAC1: OFDX port map (D=>iData_in(1), CE=>iDACMODE_SEL, C=>iWRn_clk, Q=>DACM4);
OFDDAC2: OFDX port map (D=>iData_in(0), CE=>iDACRESET_SEL, C=>iWRn_clk, Q=>DA_RESETn);
--BEGIN mute control section
FDDAC3: FDCE port map (D=>iData_in(0), CE=>iDACMUTE_SEL, CLR=>logic_zero, C=>iWRn_clk, Q=>iDAC_MUTEn);
iMUTE_DAn <= iMUTEn and iDAC_MUTEn and iADCAL_OFF;
FDMUTE0: FDCE port map (D=>iData_in(0), CE=>iSSI_MUTE0, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSIMUTE0n);
FDMUTE1: FDCE port map (D=>iData_in(0), CE=>iSSI_MUTE1, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSIMUTE1n);
FDMUTE2: FDCE port map (D=>iData_in(0), CE=>iSSI_MUTE2, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSIMUTE2n);
FDMUTE3: FDCE port map (D=>iData_in(0), CE=>iSSI_MUTE3, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSIMUTE3n);
FDMUTE4: FDCE port map (D=>iData_in(0), CE=>iAES_MUTE, CLR=>logic_zero, C=>iWRn_clk, Q=>iAESMUTEn);
iMUTE_RD <= not (iDACMUTE_SEL and not iRDn);
BTSSI0MUTE: BUFT port map (I=>iSSIMUTE0n, T=>iMUTE_RD, O=>iData_out(2));
BTSSI1MUTE: BUFT port map (I=>iSSIMUTE1n, T=>iMUTE_RD, O=>iData_out(3));
BTSSI2MUTE: BUFT port map (I=>iSSIMUTE2n, T=>iMUTE_RD, O=>iData_out(4));
BTSSI3MUTE: BUFT port map (I=>iSSIMUTE3n, T=>iMUTE_RD, O=>iData_out(5));
BTDACMUTE: BUFT port map (I=>iDAC_MUTEn, T=>iMUTE_RD, O=>iData_out(6));
BTAESMUTE: BUFT port map (I=>iAESMUTEn, T=>iMUTE_RD, O=>iData_out(7));
-- align mute signals up with frame sync
process (iFS1_clk)
begin
if (iFS1_clk'event and iFS1_clk='1') then
iMuteSSI0n <= iSSIMUTE0n and iMUTEn and iADCAL_OFF;
iMuteSSI1n <= iSSIMUTE1n and iMUTEn and iADCAL_OFF;
iMuteSSI2n <= iSSIMUTE2n and iMUTEn and iADCAL_OFF;
iMuteSSI3n <= iSSIMUTE3n and iMUTEn and iADCAL_OFF;
iMuteAESn <= iAESMUTEn and iMUTEn and iADCAL_OFF;
end if;
end process;
--END mute control section
--this section and the next six control the data routing
--DAC routing
FDDAC0: FDCE port map (D=>iData_in(0), CE=>iDAC_REG, CLR=>logic_zero, C=>iWRn_clk, Q=>iDAC_SEL(0));
FDDAC1: FDCE port map (D=>iData_in(1), CE=>iDAC_REG, CLR=>logic_zero, C=>iWRn_clk, Q=>iDAC_SEL(1));
FDDAC2: FDCE port map (D=>iData_in(2), CE=>iDAC_REG, CLR=>logic_zero, C=>iWRn_clk, Q=>iDAC_SEL(2));
process (iDAC_SEL, iSSI_DOUT, iAD_DATA1, iAD_DATA2, iAES_DIN, iSine_ser_data)
begin
case iDAC_SEL is
when "000" => iDA_DATA <= iSSI_DOUT(0);
when "001" => iDA_DATA <= iSSI_DOUT(1);
when "010" => iDA_DATA <= iSSI_DOUT(2);
when "011" => iDA_DATA <= iSSI_DOUT(3);
when "100" => iDA_DATA <= iAD_DATA1;
when "101" => iDA_DATA <= iAES_DIN;
when "110" => iDA_DATA <= iAD_DATA2;
when "111" => iDA_DATA <= iSine_ser_data;
when others => iDA_DATA <= iSine_ser_data;
end case;
end process; -- end select DAC data process
iDAC_RD <= not (iDAC_REG and not iRDn);
BTDAC0: BUFT port map (I=>iDAC_SEL(0), T=>iDAC_RD, O=>iData_out(0));
BTDAC1: BUFT port map (I=>iDAC_SEL(1), T=>iDAC_RD, O=>iData_out(1));
BTDAC2: BUFT port map (I=>iDAC_SEL(2), T=>iDAC_RD, O=>iData_out(2));
--AES routing
FDAES0: FDCE port map (D=>iData_in(0), CE=>iAES_REG, CLR=>logic_zero, C=>iWRn_clk, Q=>iAES_SEL(0));
FDAES1: FDCE port map (D=>iData_in(1), CE=>iAES_REG, CLR=>logic_zero, C=>iWRn_clk, Q=>iAES_SEL(1));
FDAES2: FDCE port map (D=>iData_in(2), CE=>iAES_REG, CLR=>logic_zero, C=>iWRn_clk, Q=>iAES_SEL(2));
process (iAES_SEL, iSSI_DOUT, iAD_DATA1, iAD_DATA2, iAES_DIN, iSine_ser_data)
begin
case iAES_SEL is
when "000" => iAES_DOUT <= iSSI_DOUT(0);
when "001" => iAES_DOUT <= iSSI_DOUT(1);
when "010" => iAES_DOUT <= iSSI_DOUT(2);
when "011" => iAES_DOUT <= iSSI_DOUT(3);
when "100" => iAES_DOUT <= iAD_DATA1;
when "101" => iAES_DOUT <= iAES_DIN;
when "110" => iAES_DOUT <= iAD_DATA2;
when "111" => iAES_DOUT <= iSine_ser_data;
when others => iAES_DOUT <= iSine_ser_data;
end case;
end process; -- end select AES data process
iAES_DOUT_M <= iAES_DOUT and iMUTEAESn;
iAES_RD <= not (iAES_REG and not iRDn);
BTAES0: BUFT port map (I=>iAES_SEL(0), T=>iAES_RD, O=>iData_out(0));
BTAES1: BUFT port map (I=>iAES_SEL(1), T=>iAES_RD, O=>iData_out(1));
BTAES2: BUFT port map (I=>iAES_SEL(2), T=>iAES_RD, O=>iData_out(2));
--SSI0 routing
FDSSI00: FDCE port map (D=>iData_in(0), CE=>iSSI_REG0, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSI_SEL0(0));
FDSSI01: FDCE port map (D=>iData_in(1), CE=>iSSI_REG0, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSI_SEL0(1));
FDSSI02: FDCE port map (D=>iData_in(2), CE=>iSSI_REG0, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSI_SEL0(2));
process (iSSI_SEL0, iSSI_DOUT, iAD_DATA1, iAD_DATA2, iAES_DIN, iSine_ser_data)
begin
case iSSI_SEL0 is
when "000" => iSSI_DIN(0) <= iSSI_DOUT(0);
when "001" => iSSI_DIN(0) <= iSSI_DOUT(1);
when "010" => iSSI_DIN(0) <= iSSI_DOUT(2);
when "011" => iSSI_DIN(0) <= iSSI_DOUT(3);
when "100" => iSSI_DIN(0) <= iAD_DATA1;
when "101" => iSSI_DIN(0) <= iAES_DIN;
when "110" => iSSI_DIN(0) <= iAD_DATA2;
when "111" => iSSI_DIN(0) <= iSine_ser_data;
when others => iSSI_DIN(0) <= iSine_ser_data;
end case;
end process; -- end select AES data process
iSSI_DIN_M(0) <= iSSI_DIN(0) and iMUTESSI0n;
iSSI0_RD <= not (iSSI_REG0 and not iRDn);
BTSSI00: BUFT port map (I=>iSSI_SEL0(0), T=>iSSI0_RD, O=>iData_out(0));
BTSSI01: BUFT port map (I=>iSSI_SEL0(1), T=>iSSI0_RD, O=>iData_out(1));
BTSSI02: BUFT port map (I=>iSSI_SEL0(2), T=>iSSI0_RD, O=>iData_out(2));
--SSI1 routing
FDSSI10: FDCE port map (D=>iData_in(0), CE=>iSSI_REG1, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSI_SEL1(0));
FDSSI11: FDCE port map (D=>iData_in(1), CE=>iSSI_REG1, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSI_SEL1(1));
FDSSI12: FDCE port map (D=>iData_in(2), CE=>iSSI_REG1, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSI_SEL1(2));
process (iSSI_SEL1, iSSI_DOUT, iAD_DATA1, iAD_DATA2, iAES_DIN, iSine_ser_data)
begin
case iSSI_SEL1 is
when "000" => iSSI_DIN(1) <= iSSI_DOUT(0);
when "001" => iSSI_DIN(1) <= iSSI_DOUT(1);
when "010" => iSSI_DIN(1) <= iSSI_DOUT(2);
when "011" => iSSI_DIN(1) <= iSSI_DOUT(3);
when "100" => iSSI_DIN(1) <= iAD_DATA1;
when "101" => iSSI_DIN(1) <= iAES_DIN;
when "110" => iSSI_DIN(1) <= iAD_DATA2;
when "111" => iSSI_DIN(1) <= iSine_ser_data;
when others => iSSI_DIN(1) <= iSine_ser_data;
end case;
end process; -- end select AES data process
iSSI_DIN_M(1) <= iSSI_DIN(1) and iMUTESSI1n;
iSSI1_RD <= not (iSSI_REG1 and not iRDn);
BTSSI10: BUFT port map (I=>iSSI_SEL1(0), T=>iSSI1_RD, O=>iData_out(0));
BTSSI11: BUFT port map (I=>iSSI_SEL1(1), T=>iSSI1_RD, O=>iData_out(1));
BTSSI12: BUFT port map (I=>iSSI_SEL1(2), T=>iSSI1_RD, O=>iData_out(2));
--SSI2 routing
FDSSI20: FDCE port map (D=>iData_in(0), CE=>iSSI_REG2, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSI_SEL2(0));
FDSSI21: FDCE port map (D=>iData_in(1), CE=>iSSI_REG2, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSI_SEL2(1));
FDSSI22: FDCE port map (D=>iData_in(2), CE=>iSSI_REG2, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSI_SEL2(2));
process (iSSI_SEL2, iSSI_DOUT, iAD_DATA1, iAD_DATA2, iAES_DIN, iSine_ser_data)
begin
case iSSI_SEL2 is
when "000" => iSSI_DIN(2) <= iSSI_DOUT(0);
when "001" => iSSI_DIN(2) <= iSSI_DOUT(1);
when "010" => iSSI_DIN(2) <= iSSI_DOUT(2);
when "011" => iSSI_DIN(2) <= iSSI_DOUT(3);
when "100" => iSSI_DIN(2) <= iAD_DATA1;
when "101" => iSSI_DIN(2) <= iAES_DIN;
when "110" => iSSI_DIN(2) <= iAD_DATA2;
when "111" => iSSI_DIN(2) <= iSine_ser_data;
when others => iSSI_DIN(2) <= iSine_ser_data;
end case;
end process; -- end select AES data process
iSSI_DIN_M(2) <= iSSI_DIN(2) and iMUTESSI2n;
iSSI2_RD <= not (iSSI_REG2 and not iRDn);
BTSSI20: BUFT port map (I=>iSSI_SEL2(0), T=>iSSI2_RD, O=>iData_out(0));
BTSSI21: BUFT port map (I=>iSSI_SEL2(1), T=>iSSI2_RD, O=>iData_out(1));
BTSSI22: BUFT port map (I=>iSSI_SEL2(2), T=>iSSI2_RD, O=>iData_out(2));
--SSI3 routing
FDSSI30: FDCE port map (D=>iData_in(0), CE=>iSSI_REG3, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSI_SEL3(0));
FDSSI31: FDCE port map (D=>iData_in(1), CE=>iSSI_REG3, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSI_SEL3(1));
FDSSI32: FDCE port map (D=>iData_in(2), CE=>iSSI_REG3, CLR=>logic_zero, C=>iWRn_clk, Q=>iSSI_SEL3(2));
process (iSSI_SEL3, iSSI_DOUT, iAD_DATA1, iAD_DATA2, iAES_DIN, iSine_ser_data)
begin
case iSSI_SEL3 is
when "000" => iSSI_DIN(3) <= iSSI_DOUT(0);
when "001" => iSSI_DIN(3) <= iSSI_DOUT(1);
when "010" => iSSI_DIN(3) <= iSSI_DOUT(2);
when "011" => iSSI_DIN(3) <= iSSI_DOUT(3);
when "100" => iSSI_DIN(3) <= iAD_DATA1;
when "101" => iSSI_DIN(3) <= iAES_DIN;
when "110" => iSSI_DIN(3) <= iAD_DATA2;
when "111" => iSSI_DIN(3) <= iSine_ser_data;
when others => iSSI_DIN(3) <= iSine_ser_data;
end case;
end process; -- end select AES data process
iSSI_DIN_M(3) <= iSSI_DIN(3) and iMUTESSI3n;
iSSI3_RD <= not (iSSI_REG3 and not iRDn);
BTSSI30: BUFT port map (I=>iSSI_SEL3(0), T=>iSSI3_RD, O=>iData_out(0));
BTSSI31: BUFT port map (I=>iSSI_SEL3(1), T=>iSSI3_RD, O=>iData_out(1));
BTSSI32: BUFT port map (I=>iSSI_SEL3(2), T=>iSSI3_RD, O=>iData_out(2));
--BEGIN sine wave table control section
IFD0: IFD port map (D=>FS1_OUT, C=>iBITCLK, Q=>iFS1_dly1);
FDDLY2: FDCE port map (D=>iFS1_dly1, CE=>logic_one, CLR=>logic_zero, C=>iBITCLK, Q=>iFS1_dly2);
--look for falling edge of FS1
iFS1_edge <= (not iFS1_dly1 and iFS1_dly2); --demarcates falling edge
-- do the serial sinewave counter
process (iBitclkn)
begin
if (iBitclkn'event and iBitclkn='1') then
if iFS1_edge = '1' then
iMux_cnt <= "00001";
else
iMux_cnt <= iMux_cnt + 1;
end if;
end if;
end process;
-- do the sinewave address counter, phase is irrelevant
process (iFS1_clk)
begin
if (iFS1_clk'event and iFS1_clk='1') then
iSine_cnt_str <= iSine_cnt_str + iFreq_step;
end if;
end process;
sine1 : sinerom port map (A =>iSine_cnt_str , DO => iTable_data);
--need to convert parallel to serial data
process (iBitclkn, iSine_data, iTable_data, iMux_cnt)
begin
if (iBitclkn'event and iBitclkn='1') then
if iSine_enable = '1' then
if (iMux_cnt = "11111") then
iSine_data <= iTable_data;
else
iSine_data <= iSine_data(22 downto 0) & '0'; --shift data
end if;
end if;
end if;
end process;
--delay serial stream by half word cycle to align channels properly
L3: RAML32X1S port map (A => iMux_cnt, DO => iSine_ser_data , DI => iSine_data(23) , WR_EN => logic_one, WR_CLK => iBitclkn);
FDGAIN0: FDCE port map (D=>iData_in(0), CE=>iGAIN_SEL, CLR=>logic_zero, C=>iWRn_clk, Q=>iGain0);
FDGAIN1: FDCE port map (D=>iData_in(1), CE=>iGAIN_SEL, CLR=>logic_zero, C=>iWRn_clk, Q=>iGain1);
FDFREQ0: FDCE port map (D=>iData_in(0), CE=>iFREQ_SEL, CLR=>logic_zero, C=>iWRn_clk, Q=>iFreq_step(0));
FDFREQ1: FDCE port map (D=>iData_in(1), CE=>iFREQ_SEL, CLR=>logic_zero, C=>iWRn_clk, Q=>iFreq_step(1));
FDFREQ2: FDCE port map (D=>iData_in(2), CE=>iFREQ_SEL, CLR=>logic_zero, C=>iWRn_clk, Q=>iFreq_step(2));
FDFREQ3: FDCE port map (D=>iData_in(3), CE=>iFREQ_SEL, CLR=>logic_zero, C=>iWRn_clk, Q=>iFreq_step(3));
iGAIN_RD <= not (iGAIN_SEL and not iRDn);
iFREQ_RD <= not (iFREQ_SEL and not iRDn);
BTGAIN0: BUFT port map (I=>iGain0, T=>iGAIN_RD, O=>iData_out(0));
BTGAIN1: BUFT port map (I=>iGain1, T=>iGAIN_RD, O=>iData_out(1));
BTFREQ0: BUFT port map (I=>iFreq_step(0), T=>iFREQ_RD, O=>iData_out(0));
BTFREQ1: BUFT port map (I=>iFreq_step(1), T=>iFREQ_RD, O=>iData_out(1));
BTFREQ2: BUFT port map (I=>iFreq_step(2), T=>iFREQ_RD, O=>iData_out(2));
BTFREQ3: BUFT port map (I=>iFreq_step(3), T=>iFREQ_RD, O=>iData_out(3));
iSine_enable <= iMux_cnt(4) or iMux_cnt(3) or iMux_cnt(2) or
((not iGain1 and not iGain0) or (iMux_cnt(0) and not iGain1) or
(iMux_cnt(1) and not iGain1) or (iMux_cnt(0) and iMux_cnt(1)) or
(iMux_cnt(1) and not iGain0));
--END sine wave table control section
end CNMTestA_arch;
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