📄 cnmtesta.vhd
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signal ifADCAL_ON : STD_LOGIC;
signal iADCAL_OFF : STD_LOGIC;
--host control signals
signal iHCSn : STD_LOGIC;
signal iHENn : STD_LOGIC;
signal iHRWn : STD_LOGIC;
signal iSync_HostA : STD_LOGIC; --used to meet proper timing requirements for interfacing
signal iSync_HostB : STD_LOGIC; --to CM1 module host interface
signal iHRD_NOT : STD_LOGIC;
--miscellaneous signals
--internal oscillator signals
signal iOSC_CLOCK : STD_LOGIC;
signal iOSC_TAP4 : STD_LOGIC;
--auxiliary power pin signals
signal iAUX_POWER2 : STD_LOGIC;
signal iAUX_POWER3 : STD_LOGIC;
--reserved pin signals
signal iRSVD : STD_LOGIC_VECTOR (4 downto 1);
--used to test SCI_CLK
signal iSCI_CLK : STD_LOGIC;
--these are the ASCII version identifiers
signal iVMAJOR_RD : STD_LOGIC;
signal iVMINOR_RD : STD_LOGIC;
signal iVREV_RD : STD_LOGIC;
--define level signals here
signal logic_one: STD_LOGIC;
signal logic_zero: STD_LOGIC;
begin
logic_one <= '1'; --initialize level signals
logic_zero <= '0';
--MCU control signals here
IBWR0: IBUF port map (I=>WRn, O=>iWRn_in);
IBGWR0: BUFG port map (I=>WRn, O=>iWRn_clk);
IBRD: IBUF port map (I=>RDn, O=>iRDn);
iHRD_NOT <= iRDn or not iAU(7) or iHOST_SEL;
IBALE: IBUF port map (I=>ALE, O=>iALE_in);
IBGALE: BUFG port map (I=>ALE, O=>iALE);
OBALE: OBUF port map (I=>iALE_in, O=>ALE_X);
--Audio clock signals
IBFS1: IBUF port map (I=>FS1_OUT, O=>iFS1_in);
IBGFS1: BUFG port map (I=>FS1_OUT, O=>iFS1_clk);
IBGBIT: BUFG port map (I=>BITCLK, O=>iBitclk);
iBitclkn <= not iBitclk;
IBFBIN: IBUF port map (I=>BITCLK, O=>iBitclk_in);
OBFS5: OBUF port map (I=>iBitclk_in, O=>BITCLK_X);
-- address/data bus I/O buffer signals.
--data I/O buffers
OBTD0: OBUFT port map (I=>iData_out(0), T=>iHRD_NOT, O=>AD(0));
IBFAD0: IBUF port map (I=>AD(0), O=>iData_in(0));
OBTD1: OBUFT port map (I=>iData_out(1), T=>iHRD_NOT, O=>AD(1));
IBFAD1: IBUF port map (I=>AD(1), O=>iData_in(1));
OBTD2: OBUFT port map (I=>iData_out(2), T=>iHRD_NOT, O=>AD(2));
IBFAD2: IBUF port map (I=>AD(2), O=>iData_in(2));
OBTD3: OBUFT port map (I=>iData_out(3), T=>iHRD_NOT, O=>AD(3));
IBFAD3: IBUF port map (I=>AD(3), O=>iData_in(3));
OBTD4: OBUFT port map (I=>iData_out(4), T=>iHRD_NOT, O=>AD(4));
IBFAD4: IBUF port map (I=>AD(4), O=>iData_in(4));
OBTD5: OBUFT port map (I=>iData_out(5), T=>iHRD_NOT, O=>AD(5));
IBFAD5: IBUF port map (I=>AD(5), O=>iData_in(5));
OBTD6: OBUFT port map (I=>iData_out(6), T=>iHRD_NOT, O=>AD(6));
IBFAD6: IBUF port map (I=>AD(6), O=>iData_in(6));
OBTD7: OBUFT port map (I=>iData_out(7), T=>iHRD_NOT, O=>AD(7));
IBFAD7: IBUF port map (I=>AD(7), O=>iData_in(7));
--latch the lower address data bus from MCU muxed data/address bus
iALEn <= not iALE;
OFDD0: OFD port map (D=>iData_in(0), C=>iALEn, Q=>AL(0)); --use I/O flip-flop
IBFAL0: IBUF port map (I=>AL(0), O=>iAL_in(0));
OFDD1: OFD port map (D=>iData_in(1), C=>iALEn, Q=>AL(1)); --use I/O flip-flop
IBFAL1: IBUF port map (I=>AL(1), O=>iAL_in(1));
OFDD2: OFD port map (D=>iData_in(2), C=>iALEn, Q=>AL(2)); --use I/O flip-flop
IBFAL2: IBUF port map (I=>AL(2), O=>iAL_in(2));
OFDD3: OFD port map (D=>iData_in(3), C=>iALEn, Q=>AL(3)); --use I/O flip-flop
IBFAL3: IBUF port map (I=>AL(3), O=>iAL_in(3));
OFDD4: OFD port map (D=>iData_in(4), C=>iALEn, Q=>AL(4)); --use I/O flip-flop
IBFAL4: IBUF port map (I=>AL(4), O=>iAL_in(4));
OFDD5: OFD port map (D=>iData_in(5), C=>iALEn, Q=>AL(5)); --use I/O flip-flop
IBFAL5: IBUF port map (I=>AL(5), O=>iAL_in(5));
OFDD6: OFD port map (D=>iData_in(6), C=>iALEn, Q=>AL(6)); --use I/O flip-flop
IBFAL6: IBUF port map (I=>AL(6), O=>iAL_in(6));
OFDD7: OFD port map (D=>iData_in(7), C=>iALEn, Q=>AL(7)); --use I/O flip-flop
IBFAL7: IBUF port map (I=>AL(7), O=>iAL_in(7));
--addr3 for CM-2
OBADDR3: OBUF port map (I=>iAL_in(3), O=>ADDR3);
--bring in the upper address lines
IBAU0: IBUF port map (I=>AU(0), O=>iAU(0));
IBAU1: IBUF port map (I=>AU(1), O=>iAU(1));
IBAU2: IBUF port map (I=>AU(2), O=>iAU(2));
IBAU3: IBUF port map (I=>AU(3), O=>iAU(3));
IBAU4: IBUF port map (I=>AU(4), O=>iAU(4));
IBAU5: IBUF port map (I=>AU(5), O=>iAU(5));
IBAU6: IBUF port map (I=>AU(6), O=>iAU(6));
IBAU7: IBUF port map (I=>AU(7), O=>iAU(7));
--bring in the SSI data
IBSSI0: IBUF port map (I=>SSI_DOUT(0), O=>iSSI_DOUT(0));
IBSSI1: IBUF port map (I=>SSI_DOUT(1), O=>iSSI_DOUT(1));
IBSSI2: IBUF port map (I=>SSI_DOUT(2), O=>iSSI_DOUT(2));
IBSSI3: IBUF port map (I=>SSI_DOUT(3), O=>iSSI_DOUT(3));
--SSI output data buffers
OBSSI0: OBUF port map (I=>iSSI_DIN_M(0), O=>SSI_DIN(0));
OBSSI1: OBUF port map (I=>iSSI_DIN_M(1), O=>SSI_DIN(1));
OBSSI2: OBUF port map (I=>iSSI_DIN_M(2), O=>SSI_DIN(2));
OBSSI3: OBUF port map (I=>iSSI_DIN_M(3), O=>SSI_DIN(3));
--other serial data I/O buffers
IBADC1: IBUF port map (I=>AD_DATA1, O=>iAD_DATA1);
IBADC2: IBUF port map (I=>AD_DATA2, O=>iAD_DATA2);
OBDAC: OBUF port map (I=>iDA_DATA, O=>DA_DATA);
IBAES: IBUF port map (I=>AES_DIN, O=>iAES_DIN);
OBAES: OBUF port map (I=>iAES_DOUT_M, O=>AES_DOUT);
--mute control buffers
OBMUTE: OBUF port map (I=>iMUTE_DAn, O=>MUTE_DAn);
IBMUTE: IBUF port map (I=>MUTEn, O=>iMUTEn);
--host control buffers
OBHCS: OBUF port map (I=>iHCSn, O=>HCSn);
OBHEN: OBUF port map (I=>iHCSn, O=>HENn);
OBHRW: OBUF port map (I=>iHRWn, O=>HRWn);
--LED output buffers
OBLEDGRN: OBUF port map (I=>iLEDGRN, O=>LEDGRN);
OBLEDRED: OBUF port map (I=>iLEDRED, O=>LEDRED);
OBLEDYLW: OBUF port map (I=>iLEDYLW, O=>LEDYLW);
--auxiliary power and reserved pin buffers
IBAUX2: IBUF port map (I=>AUX_POWER2, O=>iAUX_POWER2);
IBAUX3: IBUF port map (I=>AUX_POWER3, O=>iAUX_POWER3);
IBRSVD1: IBUF port map (I=>RSVD(1), O=>iRSVD(1));
IBRSVD2: IBUF port map (I=>RSVD(2), O=>iRSVD(2));
IBRSVD3: IBUF port map (I=>RSVD(3), O=>iRSVD(3));
IBRSVD4: IBUF port map (I=>RSVD(4), O=>iRSVD(4));
-- begin address decode
-- decode upper 8 bits.
xADDR <= '1' when iAU = "10000000" else '0'; -- receive control registers
--LED on/off and blink control selects.
iLEDGRN_SEL <= '1' when (iAL_in = "00000000" and xADDR = '1') else '0';
iLEDRED_SEL <= '1' when (iAL_in = "00000001" and xADDR = '1') else '0';
iLEDYLW_SEL <= '1' when (iAL_in = "00000010" and xADDR = '1') else '0';
iBLINKGRN_SEL <= '1' when (iAL_in = "00000100" and xADDR = '1') else '0';
iBLINKRED_SEL <= '1' when (iAL_in = "00000101" and xADDR = '1') else '0';
iBLINKYLW_SEL <= '1' when (iAL_in = "00000110" and xADDR = '1') else '0';
iDAC_REG <= '1' when (iAL_in = "00001000" and xADDR = '1') else '0';
iDACMUTE_SEL <= '1' when (iAL_in = "00001001" and xADDR = '1') else '0';
iDACMODE_SEL <= '1'when (iAL_in = "00001010" and xADDR = '1') else '0';
iDACRESET_SEL <= '1'when (iAL_in = "00001011" and xADDR = '1') else '0';
iADC_CAL_SEL <= '1' when (iAL_in = "00010000" and xADDR = '1') else '0';
iADC_SLAVE <= '1' when (iAL_in = "00010001" and xADDR = '1') else '0';
iAES_REG <= '1' when (iAL_in = "00011000" and xADDR = '1') else '0';
iAES_MUTE <= '1' when (iAL_in = "00011001" and xADDR = '1') else '0';
iSSI_REG0 <= '1' when (iAL_in = "00100000" and xADDR = '1') else '0';
iSSI_MUTE0 <= '1' when (iAL_in = "00100001" and xADDR = '1') else '0';
iSSI_REG1 <= '1' when (iAL_in = "00101000" and xADDR = '1') else '0';
iSSI_MUTE1 <= '1' when (iAL_in = "00101001" and xADDR = '1') else '0';
iSSI_REG2 <= '1' when (iAL_in = "00110000" and xADDR = '1') else '0';
iSSI_MUTE2 <= '1' when (iAL_in = "00110001" and xADDR = '1') else '0';
iSSI_REG3 <= '1' when (iAL_in = "00111000" and xADDR = '1') else '0';
iSSI_MUTE3 <= '1' when (iAL_in = "00111001" and xADDR = '1') else '0';
iHOST_SEL <= '1' when (iAL_in(7 downto 4) = "0100" and xADDR = '1') else '0';
iHOST_RESET <= '1' when (iAL_in = "01010001" and xADDR = '1') else '0';
iRSVD_SEL <= '1' when (iAL_in = "01010000" and xADDR = '1') else '0';
iAUX_SEL <= '1' when (iAL_in = "01011000" and xADDR = '1') else '0';
iVMAJOR_SEL <= '1' when (iAL_in = "01100000" and xADDR = '1') else '0';
iVMINOR_SEL <= '1' when (iAL_in = "01100001" and xADDR = '1') else '0';
iVREV_SEL <= '1' when (iAL_in = "01100010" and xADDR = '1') else '0';
iGAIN_SEL <= '1' when (iAL_in = "01110000" and xADDR = '1') else '0';
iFREQ_SEL <= '1' when (iAL_in = "01111000" and xADDR = '1') else '0';
-- end address decode
--BEGIN LED control section
iLEDGRN_RD <= not (iLEDGRN_SEL and not iRDn);
iLEDRED_RD <= not (iLEDRED_SEL and not iRDn);
iLEDYLW_RD <= not (iLEDYLW_SEL and not iRDn);
--write (and Read) LED and blink control bits
FDLEDGRN: FDCE port map (D=>iData_in(0), CE=>iLEDGRN_SEL, CLR=>logic_zero, C=>iWRn_clk, Q=>iTEMP_LEDGRN);
FDLEDRED: FDCE port map (D=>iData_in(0), CE=>iLEDRED_SEL, CLR=>logic_zero, C=>iWRn_clk, Q=>iTEMP_LEDRED);
FDLEDYLW: FDCE port map (D=>iData_in(0), CE=>iLEDYLW_SEL, CLR=>logic_zero, C=>iWRn_clk, Q=>iTEMP_LEDYLW);
BTLEDGRN: BUFT port map (I=>iTEMP_LEDGRN, T=>iLEDGRN_RD, O=>iData_out(0));
BTLEDRED: BUFT port map (I=>iTEMP_LEDRED, T=>iLEDRED_RD, O=>iData_out(0));
BTLEDYLW: BUFT port map (I=>iTEMP_LEDYLW, T=>iLEDYLW_RD, O=>iData_out(0));
FDLED4: FDCE port map (D=>iData_in(0), CE=>iBLINKGRN_SEL, CLR=>logic_zero, C=>iWRn_clk, Q=>iLEDBLINKGRN);
FDLED5: FDCE port map (D=>iData_in(0), CE=>iBLINKRED_SEL, CLR=>logic_zero, C=>iWRn_clk, Q=>iLEDBLINKRED);
FDLED6: FDCE port map (D=>iData_in(0), CE=>iBLINKYLW_SEL, CLR=>logic_zero, C=>iWRn_clk, Q=>iLEDBLINKYLW);
--use the internal oscillator for blink control
MYOSC: OSC4 port map (F8M=>open, F500K=>open, F16K=>open, F490=>open, F15=>iOSC_TAP4);
OSCBUF: BUFG port map (I=>iOSC_TAP4, O=>iOSC_CLOCK);
--want blink rate between 1 and 2 Hz.
-- this is the blink rate counter
process (iOSC_CLOCK)
begin
if iOSC_CLOCK'event and iOSC_CLOCK='1' then
iBLINK_CNT <= iBLINK_CNT + 1;
end if;
end process;
iLEDGRN <= (not iLEDBLINKGRN and iTEMP_LEDGRN) or (iBLINK_CNT(2) and iLEDBLINKGRN);
iLEDRED <= (not iLEDBLINKRED and iTEMP_LEDRED) or (iBLINK_CNT(2) and iLEDBLINKRED);
iLEDYLW <= (not iLEDBLINKYLW and iTEMP_LEDYLW) or (iBLINK_CNT(2) and iLEDBLINKYLW);
--END of LED section
--BEGIN HOST control signals
process (iWRn_clk, iSync_HostB)
begin
if iSync_HostB = '1' then
iSync_HostA <= '0';
elsif (iWRn_clk'event and iWRn_clk='0') then --falling edge
iSync_HostA <= iHOST_SEL;
end if;
end process;
process (iWRn_clk, iHOST_SEL, iSync_HostA)
begin
if iSync_HostA = '0' then
iSync_HostB <= '0';
elsif (iWRn_clk'event and iWRn_clk='1') then
iSync_HostB <= iHOST_SEL;
end if;
end process;
OFDHOST0: OFDX port map (D=>iData_in(0), CE=>iHOST_RESET, C=>iWRn_clk, Q=>HRESETn);
iHCSn <= not ((not iRDn or (not iWRn_in and iSync_HostA)) and iHOST_SEL);
iHRWn <= not ((not iWRn_in and iHOST_SEL) or iSync_HostA);
--END HOST control signals
--BEGIN auxiliary power pin test section
OFDAUX0: OFDX port map (D=>iData_in(0), CE=>iAUX_SEL, C=>iWRn_clk, Q=>AUX_POWER0);
OFDAUX1: OFDX port map (D=>iData_in(1), CE=>iAUX_SEL, C=>iWRn_clk, Q=>AUX_POWER1);
iAUX_RD <= not (iAUX_SEL and not iRDn);
BTAUX0: BUFT port map (I=>iAUX_POWER2, T=>iAUX_RD, O=>iData_out(0));
BTAUX: BUFT port map (I=>iAUX_POWER3, T=>iAUX_RD, O=>iData_out(1));
--END auxiliary power pin test section
--master/slave control bit flip-flop
OFDSLAVE: OFDX port map (D=>iData_in(0), CE=>iADC_SLAVE, C=>iWRn_clk, Q=>SLAVE);
--BEGIN reserved bit section
iRSVD_RD <= not (iRSVD_SEL and not iRDn);
BTRSVD1: BUFT port map (I=>iRSVD(1), T=>iRSVD_RD, O=>iData_out(1));
BTRSVD2: BUFT port map (I=>iRSVD(2), T=>iRSVD_RD, O=>iData_out(2));
BTRSVD3: BUFT port map (I=>iRSVD(3), T=>iRSVD_RD, O=>iData_out(3));
BTRSVD4: BUFT port map (I=>iRSVD(4), T=>iRSVD_RD, O=>iData_out(4));
--END reserved bit section
--BEGIN the firmware version ID section
iVMAJOR_RD <= not (iVMAJOR_SEL and not iRDn);
BTVMAJ0: BUFT port map (I=>logic_one, T=>iVMAJOR_RD, O=>iData_out(0));
BTVMAJ1: BUFT port map (I=>logic_zero, T=>iVMAJOR_RD, O=>iData_out(1));
BTVMAJ2: BUFT port map (I=>logic_zero, T=>iVMAJOR_RD, O=>iData_out(2));
BTVMAJ3: BUFT port map (I=>logic_zero, T=>iVMAJOR_RD, O=>iData_out(3));
BTVMAJ4: BUFT port map (I=>logic_one, T=>iVMAJOR_RD, O=>iData_out(4));
BTVMAJ5: BUFT port map (I=>logic_one, T=>iVMAJOR_RD, O=>iData_out(5));
BTVMAJ6: BUFT port map (I=>logic_zero, T=>iVMAJOR_RD, O=>iData_out(6));
BTVMAJ7: BUFT port map (I=>logic_zero, T=>iVMAJOR_RD, O=>iData_out(7));
iVMINOR_RD <= not (iVMINOR_SEL and not iRDn);
BTVMIN0: BUFT port map (I=>logic_one, T=>iVMINOR_RD, O=>iData_out(0));
BTVMIN1: BUFT port map (I=>logic_one, T=>iVMINOR_RD, O=>iData_out(1));
BTVMIN2: BUFT port map (I=>logic_zero, T=>iVMINOR_RD, O=>iData_out(2));
BTVMIN3: BUFT port map (I=>logic_zero, T=>iVMINOR_RD, O=>iData_out(3));
BTVMIN4: BUFT port map (I=>logic_one, T=>iVMINOR_RD, O=>iData_out(4));
BTVMIN5: BUFT port map (I=>logic_one, T=>iVMINOR_RD, O=>iData_out(5));
BTVMIN6: BUFT port map (I=>logic_zero, T=>iVMINOR_RD, O=>iData_out(6));
BTVMIN7: BUFT port map (I=>logic_zero, T=>iVMINOR_RD, O=>iData_out(7));
iVREV_RD <= not (iVREV_SEL and not iRDn);
BTVREV0: BUFT port map (I=>logic_one, T=>iVREV_RD, O=>iData_out(0));
BTVREV1: BUFT port map (I=>logic_zero, T=>iVREV_RD, O=>iData_out(1));
BTVREV2: BUFT port map (I=>logic_zero, T=>iVREV_RD, O=>iData_out(2));
BTVREV3: BUFT port map (I=>logic_zero, T=>iVREV_RD, O=>iData_out(3));
BTVREV4: BUFT port map (I=>logic_one, T=>iVREV_RD, O=>iData_out(4));
BTVREV5: BUFT port map (I=>logic_one, T=>iVREV_RD, O=>iData_out(5));
BTVREV6: BUFT port map (I=>logic_zero, T=>iVREV_RD, O=>iData_out(6));
BTVREV7: BUFT port map (I=>logic_zero, T=>iVREV_RD, O=>iData_out(7));
--END firmware version ID section
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