📄 cnmtesta.vhd
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--=========================================================================
--CNMTestA.vhd
--Version 1.1.1
--Version 1.1.2 Added SCI_CLK to MCU_P35 connection
--Version 1.1.3 Added HENn
--Version 1.2.0 Replace RSVD0 with ADDR3 for CM2 host port
-- Needed to change host reset decoding for ADDR3 addition
--Version 1.3.0 Added gain selection for sinewave
--Version 1.3.1 swapped AES and ADC2 routing
--Copyright (C) 2001 by Cirrus Logic Incorporated All Rights Reserved
--==========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library synopsys;
use synopsys.attributes.all;
entity CNMTestA is
port (
--inputs
AD_DATA1: in STD_LOGIC; -- regular PCM data from the ADC
AD_DATA2: in STD_LOGIC; -- same as AD_DATA1 but with group delay
AES_DIN: in STD_LOGIC; -- data from AES receiver (sample rate converted)
ALE: in STD_LOGIC; -- ALE signal from 8051
AU: in STD_LOGIC_VECTOR (7 downto 0); -- upper address signals from 8051
FS1_OUT: in STD_LOGIC; -- sample rate clock from CN module - not used
--FS512_OUT: in STD_LOGIC; -- two times bit rate clock from CN module
BITCLK: in STD_LOGIC;
MUTEn: in STD_LOGIC; -- mute signal from CN module
RDn: in STD_LOGIC; -- Read control signal from 8051
SSI_DOUT: in STD_LOGIC_VECTOR (3 downto 0); -- audio data output to CN module
WRn: in STD_LOGIC; -- write signal from CN module
AUX_POWER2: in STD_LOGIC; -- auxiliary power pins, for testing
AUX_POWER3: in STD_LOGIC;
SCI_CLK: in STD_LOGIC;
--AES_ERR: in STD_LOGIC;
--outputs
AD_CAL: out STD_LOGIC; -- ADC calibration signal
AES_DOUT: out STD_LOGIC; -- audio data to AES transmitter
DA_DATA: out STD_LOGIC; -- audio data to DAC
DA_RESETn: out STD_LOGIC; -- DAC reset signal
HCSn: out STD_LOGIC; -- CN module host chip select signal
HENn: out STD_LOGIC; -- CN module host signal - same as HCSn
HRWn: out STD_LOGIC; -- CN module host read/write signal
HRESETn: out STD_LOGIC; -- CN module host reset signal
LEDGRN: out STD_LOGIC; -- green LED control signal
LEDRED: out STD_LOGIC; -- red LED control signal
LEDYLW: out STD_LOGIC; -- yellow LED control signal
MUTE_DAn: out STD_LOGIC; -- DAC Mute signal
SLAVE: out STD_LOGIC; -- indicates whether in slave (high) or master mode.
SSI_DIN: out STD_LOGIC_VECTOR (3 downto 0); -- audio data from the CN module
AUX_POWER0: out STD_LOGIC; -- auxiliary power pins, for testing
AUX_POWER1: out STD_LOGIC;
BITCLK_X: out STD_LOGIC; -- used for debugging
ALE_X: out STD_LOGIC; -- used for debugging
ADDR3: out STD_LOGIC; -- Address line 3 for CM2, replaces RSVD0
MCU_P35: out STD_LOGIC; --these are all test pins used for debugging
DACM4: out STD_LOGIC; --controls the speed mode in the DAC
DACM2: out STD_LOGIC; -- put DAC in deemphasis mode
-- TP1: out STD_LOGIC;
-- TP2: out STD_LOGIC;
-- TP3: out STD_LOGIC;
-- TP4: out STD_LOGIC;
-- TP5: out STD_LOGIC;
-- TP6: out STD_LOGIC;
--bidirectional
AL: inout STD_LOGIC_VECTOR (7 downto 0);-- lower address signals latched from AD signals
AD: inout STD_LOGIC_VECTOR (7 downto 0);-- 8051 data lines
RSVD: inout STD_LOGIC_VECTOR (4 downto 1)-- reserved signals from the CN module
);
end CNMTestA;
architecture CNMTestA_arch of CNMTestA is
--define components here
component BUFG --global buffer
port (I: in std_logic;
O: out std_logic);
end component;
component BUFT --xilinx tri-state buffer
port (I: in std_logic;
T: in std_logic;
O: out std_logic);
end component;
component IBUF --Xilinx IOB input buffer
port (I: in std_logic;
O: out std_logic);
end component;
component FDCE --Xilinx CLB flip-flop primitive
port (D: in STD_LOGIC;
CE: in STD_LOGIC;
CLR: in STD_LOGIC;
C: in STD_LOGIC;
Q: out STD_LOGIC);
end component;
component IFD --Xilinx IOB flip flop
port (D: in STD_LOGIC;
C: in STD_LOGIC;
Q: out STD_LOGIC);
end component;
component OBUF --Xilinx IOB output buffer
port (I: in std_logic;
O: out std_logic);
end component;
component OBUFT --Xilinx IOB output tristate buffer, active low enable
port (I: in std_logic;
T: in std_logic;
O: out std_logic);
end component;
component OFD --Xilinx output buffer flip flop
port (D: in STD_LOGIC;
C: in STD_LOGIC;
Q: out STD_LOGIC);
end component;
component OFDX --Xilinx IOB output flip-flop with enable
port (D: in STD_LOGIC;
CE: in STD_LOGIC;
C: in STD_LOGIC;
Q: out STD_LOGIC);
end component;
component OSC4 --xilinx internal oscillator
port (F8M: out std_logic;
F500K: out std_logic;
F16K: out std_logic;
F490: out std_logic;
F15: out std_logic);
end component;
component sinerom --sine wave table ROM, made from logiblox
port (A: in std_logic_vector(4 downto 0);
DO: out std_logic_vector(23 downto 0));
end component;
component RAML32X1S --this is a logiblox component, used as a delay element.
PORT(
A: IN std_logic_vector(4 DOWNTO 0);
DO: OUT std_logic;
DI: IN std_logic;
WR_EN: IN std_logic;
WR_CLK: IN std_logic);
end component;
--end of component declarations
--define internal MCU control signals here
signal iAL_in : STD_LOGIC_VECTOR (7 downto 0); --lower eight address bits
signal iAU : STD_LOGIC_VECTOR (7 downto 0); --the upper eight address bits
signal xADDR : STD_LOGIC; --decoded upper 8 bits of address
signal iData_in : STD_LOGIC_VECTOR (7 downto 0); --the eight bit data INPUT bus
signal iData_out : STD_LOGIC_VECTOR (7 downto 0); --the eight bit data OUTPUT bus
signal iWRn_in : STD_LOGIC; --MCU WR signal used as logic signal
signal iWRn_clk : STD_LOGIC; --MCU WR signal used as clock signal
signal iRDn : STD_LOGIC; --MCU RD signal
signal iALE : STD_LOGIC; --MCU ALE signal
signal iALEn : STD_LOGIC; --inverted version of iALE
signal iALE_in : STD_LOGIC; --debug signal
--audio clock signals
signal iFS1_in : STD_LOGIC; --audio word clock used as logic signal
signal iFS1_clk : STD_LOGIC; --audio work clock used as clock signal
signal iBitclk_in : STD_LOGIC; --debug signal
signal iBitclk : STD_LOGIC; --audio bit clock
signal iBitclkn : STD_LOGIC; --inverted audio bit clock
signal iFS1_dly1 : STD_LOGIC; --this and next two signals are used
signal iFS1_dly2 : STD_LOGIC; --to find the rising edge of FS1
signal iFS1_edge : STD_LOGIC;
signal iMux_cnt : STD_LOGIC_VECTOR (4 downto 0); --32 bits in audio sample
--sine wave table control and data signals
signal iSine_cnt_str : STD_LOGIC_VECTOR (4 downto 0); --straight binary counter
signal iSine_data : STD_LOGIC_VECTOR (23 downto 0); --parallel sinewave data
signal iTable_data : STD_LOGIC_VECTOR (23 downto 0); --used to hold the parallel sine data
signal iSine_ser_data: STD_LOGIC; --the serial sinewave data
signal iSine_ser_dly : STD_LOGIC; --the delayed serial sinewave data
signal iSine_enable : STD_LOGIC; --enable for the serial shift register
signal iGain0 : STD_LOGIC; --sets the sinewave gain level
signal iGain1 : STD_LOGIC; --sets the sinewave gain level
signal iFreq_enable : STD_LOGIC; --enable for the serial shift register
signal iFreq_step : STD_LOGIC_VECTOR (3 downto 0); --sets the sinewave lookup step size
-- address decode signals
signal iBLINKGRN_SEL : STD_LOGIC;
signal iBLINKRED_SEL : STD_LOGIC;
signal iBLINKYLW_SEL : STD_LOGIC;
signal iLEDGRN_SEL : STD_LOGIC;
signal iLEDRED_SEL : STD_LOGIC;
signal iLEDYLW_SEL : STD_LOGIC;
signal iDAC_REG : STD_LOGIC;
signal iDACMUTE_SEL : STD_LOGIC;
signal iDACMODE_SEL : STD_LOGIC;
signal iDACRESET_SEL : STD_LOGIC;
signal iADC_CAL_SEL : STD_LOGIC;
signal iADC_SLAVE : STD_LOGIC;
signal iAES_REG : STD_LOGIC;
signal iAES_MUTE : STD_LOGIC;
signal iSSI_REG0 : STD_LOGIC;
signal iSSI_REG1 : STD_LOGIC;
signal iSSI_REG2 : STD_LOGIC;
signal iSSI_REG3 : STD_LOGIC;
signal iSSI_MUTE0 : STD_LOGIC;
signal iSSI_MUTE1 : STD_LOGIC;
signal iSSI_MUTE2 : STD_LOGIC;
signal iSSI_MUTE3 : STD_LOGIC;
signal iHOST_SEL : STD_LOGIC;
signal iHOST_RESET : STD_LOGIC;
signal iRSVD_SEL : STD_LOGIC;
signal iAUX_SEL : STD_LOGIC;
signal iVMAJOR_SEL : STD_LOGIC;
signal iVMINOR_SEL : STD_LOGIC;
signal iVREV_SEL : STD_LOGIC;
signal iGAIN_SEL : STD_LOGIC;
signal iFREQ_SEL : STD_LOGIC;
-- end of address decode signals
signal iBLINK_CNT : STD_LOGIC_VECTOR (2 downto 0); --sets the blink rate
--begin decoded read (RD) signals.
signal iLEDGRN_RD : STD_LOGIC;
signal iLEDRED_RD : STD_LOGIC;
signal iLEDYLW_RD : STD_LOGIC;
signal iRSVD_RD : STD_LOGIC;
signal iAUX_RD : STD_LOGIC;
signal iADC_CAL_RD : STD_LOGIC;
signal iGAIN_RD : STD_LOGIC;
signal iFREQ_RD : STD_LOGIC;
signal iSSI0_RD : STD_LOGIC;
signal iSSI1_RD : STD_LOGIC;
signal iSSI2_RD : STD_LOGIC;
signal iSSI3_RD : STD_LOGIC;
signal iDAC_RD : STD_LOGIC;
signal iAES_RD : STD_LOGIC;
signal iMUTE_RD : STD_LOGIC;
--miscellaneous LED internal control signals
signal iTEMP_LEDGRN : STD_LOGIC; --registered LED on/off signals
signal iTEMP_LEDRED : STD_LOGIC;
signal iTEMP_LEDYLW : STD_LOGIC;
signal iLEDBLINKGRN : STD_LOGIC; --LED blink control signals
signal iLEDBLINKRED : STD_LOGIC;
signal iLEDBLINKYLW : STD_LOGIC;
signal iLEDGRN : STD_LOGIC; --the actual LED output signal (after blink control logic)
signal iLEDRED : STD_LOGIC;
signal iLEDYLW : STD_LOGIC;
--mute signals
signal iMUTE_DAn : STD_LOGIC;
signal iMUTEn : STD_LOGIC;
signal iDAC_MUTEn : STD_LOGIC;
--intermediate mute signals
signal iSSIMUTE0n : STD_LOGIC;
signal iSSIMUTE1n : STD_LOGIC;
signal iSSIMUTE2n : STD_LOGIC;
signal iSSIMUTE3n : STD_LOGIC;
signal iAESMUTEn : STD_LOGIC;
--final mute signals
signal iMUTESSI0n : STD_LOGIC;
signal iMUTESSI1n : STD_LOGIC;
signal iMUTESSI2n : STD_LOGIC;
signal iMUTESSI3n : STD_LOGIC;
signal iMUTEAESn : STD_LOGIC;
--end of mute signals
--the following signals control the routing of audio along their respective paths
--used for mux control
signal iDAC_SEL : STD_LOGIC_VECTOR (2 downto 0);
signal iAES_SEL : STD_LOGIC_VECTOR (2 downto 0);
signal iSSI_SEL0 : STD_LOGIC_VECTOR (2 downto 0);
signal iSSI_SEL1 : STD_LOGIC_VECTOR (2 downto 0);
signal iSSI_SEL2 : STD_LOGIC_VECTOR (2 downto 0);
signal iSSI_SEL3 : STD_LOGIC_VECTOR (2 downto 0);
--serial data signals
signal iAES_DIN : STD_LOGIC;
signal iAES_DOUT : STD_LOGIC;
signal iAES_DOUT_M : STD_LOGIC;
signal iSSI_DOUT : STD_LOGIC_VECTOR (3 downto 0);
signal iSSI_DIN_M : STD_LOGIC_VECTOR (3 downto 0);
signal iSSI_DIN : STD_LOGIC_VECTOR (3 downto 0);
signal iAD_DATA1 : STD_LOGIC;
signal iAD_DATA2 : STD_LOGIC;
signal iDA_DATA : STD_LOGIC;
--ADC Calibration control signals.
signal iADC_CAL : STD_LOGIC;
signal iuADC_CAL : STD_LOGIC;
signal iADCAL_CNT : STD_LOGIC_VECTOR (7 downto 0); --used for calibration timing
signal iADCAL_ON : STD_LOGIC;
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