sinerom.vhd

控制CS18101的VDL程序,包含正弦发生器,CS18101的读写控制,串行数字音频的复合与分解

------------------------------------------------------
-- LogiBLOX ROM Module "sinerom"
-- Created by LogiBLOX version D.26
--    on Mon Jul 09 10:56:06 2001
-- Attributes 
--    MODTYPE = ROM
--    BUS_WIDTH = 24
--    DEPTH = 32
--    MEMFILE = mysine
--    TRIM = FALSE
--    STYLE = MAX_SPEED
--    USE_RPM = FALSE
------------------------------------------------------
-- This is a behaviorial model only and cannot be synthesized.
------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-- synopsys translate_off
LIBRARY logiblox;
USE logiblox.mvlutil.ALL;
USE logiblox.mvlarith.ALL;
USE logiblox.logiblox.ALL;
-- synopsys translate_on

ENTITY sinerom IS
  PORT(
    A: IN std_logic_vector(4 DOWNTO 0);
    DO: OUT std_logic_vector(23 DOWNTO 0));
END sinerom;

-- synopsys translate_off
ARCHITECTURE sim OF sinerom IS
  SIGNAL START_PULSE: std_logic := '1';
  TYPE mem_data IS ARRAY (31 DOWNTO 0) OF std_logic_vector(23 DOWNTO 0);
BEGIN
  PROCESS
  VARIABLE VD: mem_data;
  VARIABLE first_time: BOOLEAN := TRUE;
  BEGIN
    IF (first_time) THEN
      VD(0) := ('0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0');
      VD(1) := ('0','0','0','1','1','0','0','0','1','1','1','1','1','0','0','0','1','0','1','1','1','0','0','0');
      VD(2) := ('0','0','1','1','0','0','0','0','1','1','1','1','1','0','1','1','1','1','0','0','0','1','0','1');
      VD(3) := ('0','1','0','0','0','1','1','1','0','0','0','1','1','1','0','0','1','1','1','0','1','1','0','1');
      VD(4) := ('0','1','0','1','1','0','1','0','1','0','0','0','0','0','1','0','0','1','1','1','1','0','1','0');
      VD(5) := ('0','1','1','0','1','0','1','0','0','1','1','0','1','1','0','1','1','0','0','1','1','0','0','1');
      VD(6) := ('0','1','1','1','0','1','1','0','0','1','0','0','0','0','0','1','1','0','1','0','1','1','1','1');
      VD(7) := ('0','1','1','1','1','1','0','1','1','0','0','0','1','0','1','0','0','1','0','1','1','1','1','1');
      VD(8) := ('0','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1');
      VD(9) := ('0','1','1','1','1','1','0','1','1','0','0','0','1','0','1','0','0','1','0','1','1','1','1','1');
      VD(10) := ('0','1','1','1','0','1','1','0','0','1','0','0','0','0','0','1','1','0','1','0','1','1','1','1');
      VD(11) := ('0','1','1','0','1','0','1','0','0','1','1','0','1','1','0','1','1','0','0','1','1','0','0','1');
      VD(12) := ('0','1','0','1','1','0','1','0','1','0','0','0','0','0','1','0','0','1','1','1','1','0','1','0');
      VD(13) := ('0','1','0','0','0','1','1','1','0','0','0','1','1','1','0','0','1','1','1','0','1','1','0','1');
      VD(14) := ('0','0','1','1','0','0','0','0','1','1','1','1','1','0','1','1','1','1','0','0','0','1','0','1');
      VD(15) := ('0','0','0','1','1','0','0','0','1','1','1','1','1','0','0','0','1','0','1','1','1','0','0','0');
      VD(16) := ('0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0');
      VD(17) := ('1','1','1','0','0','1','1','1','0','0','0','0','0','1','1','1','0','1','0','0','1','0','0','0');
      VD(18) := ('1','1','0','0','1','1','1','1','0','0','0','0','0','1','0','0','0','0','1','1','1','0','1','1');
      VD(19) := ('1','0','1','1','1','0','0','0','1','1','1','0','0','0','1','1','0','0','0','1','0','0','1','1');
      VD(20) := ('1','0','1','0','0','1','0','1','0','1','1','1','1','1','0','1','1','0','0','0','0','1','1','0');
      VD(21) := ('1','0','0','1','0','1','0','1','1','0','0','1','0','0','1','0','0','1','1','0','0','1','1','1');
      VD(22) := ('1','0','0','0','1','0','0','1','1','0','1','1','1','1','1','0','0','1','0','1','0','0','0','1');
      VD(23) := ('1','0','0','0','0','0','1','0','0','1','1','1','0','1','0','1','1','0','1','0','0','0','0','1');
      VD(24) := ('1','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0');
      VD(25) := ('1','0','0','0','0','0','1','0','0','1','1','1','0','1','0','1','1','0','1','0','0','0','0','1');
      VD(26) := ('1','0','0','0','1','0','0','1','1','0','1','1','1','1','1','0','0','1','0','1','0','0','0','1');
      VD(27) := ('1','0','0','1','0','1','0','1','1','0','0','1','0','0','1','0','0','1','1','0','0','1','1','1');
      VD(28) := ('1','0','1','0','0','1','0','1','0','1','1','1','1','1','0','1','1','0','0','0','0','1','1','0');
      VD(29) := ('1','0','1','1','1','0','0','0','1','1','1','0','0','0','1','1','0','0','0','1','0','0','1','1');
      VD(30) := ('1','1','0','0','1','1','1','1','0','0','0','0','0','1','0','0','0','0','1','1','1','0','1','1');
      VD(31) := ('1','1','1','0','0','1','1','1','0','0','0','0','0','1','1','1','0','1','0','0','1','0','0','0');
      first_time := FALSE;
    END IF;
    IF (mvlvec_not01(A)) THEN
      DO <= ('X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X');
    ELSIF (mvlvec2int(A) > 31) THEN
      ASSERT (FALSE)
      REPORT "The value on the address line is out of range"
      SEVERITY WARNING;
      DO <= ('X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X','X');
    ELSE
      DO <= VD(mvlvec2int(A));
    END IF;
      WAIT ON A, START_PULSE;
  END PROCESS;
END sim;
-- synopsys translate_on