rom16x7.v

用verilog语言编的正弦波发生器

/****************************************************
 *	File:	rom16x7.v
 *	By:	Shuo Huang
 *	Date:	Oct. 30, 2002
 *	Description: This is a ROM model. 7-bit wide,
 *		16-word deep.
 ***************************************************/

module rom16x7 (addr, data);
    input[3:0]	addr;		// address input
    output[6:0]	data;		// data output

    reg[6:0]		rom[0:15];		// memory variable

    initial	$readmemh("rom.dat",rom);

    assign	data = rom[addr];
endmodule