📄 main.dbg
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ITEST_INT6: equ 3 ; Interrupt Test Register Bit 3
ITEST_INT8: equ 4 ; Interrupt Test Register Bit 4
ITEST_INTA: equ 5 ; Interrupt Test Register Bit 5
ITEST_INTC: equ 6 ; Interrupt Test Register Bit 6
ITEST_INTE: equ 7 ; Interrupt Test Register Bit 7
; bit position masks
mITEST_INT0: equ %00000001 ; Interrupt Test Register Bit 0
mITEST_INT2: equ %00000010 ; Interrupt Test Register Bit 1
mITEST_INT4: equ %00000100 ; Interrupt Test Register Bit 2
mITEST_INT6: equ %00001000 ; Interrupt Test Register Bit 3
mITEST_INT8: equ %00010000 ; Interrupt Test Register Bit 4
mITEST_INTA: equ %00100000 ; Interrupt Test Register Bit 5
mITEST_INTC: equ %01000000 ; Interrupt Test Register Bit 6
mITEST_INTE: equ %10000000 ; Interrupt Test Register Bit 7
;*** MTST1 - MTST1; 0x00000017 ***
MTST1: equ $00000017 ;*** MTST1 - MTST1; 0x00000017 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
MTST1_BIT0: equ 0 ; MTST1 Bit 0
MTST1_BIT1: equ 1 ; MTST1 Bit 1
MTST1_BIT2: equ 2 ; MTST1 Bit 2
MTST1_BIT3: equ 3 ; MTST1 Bit 3
MTST1_BIT4: equ 4 ; MTST1 Bit 4
MTST1_BIT5: equ 5 ; MTST1 Bit 5
MTST1_BIT6: equ 6 ; MTST1 Bit 6
MTST1_BIT7: equ 7 ; MTST1 Bit 7
; bit position masks
mMTST1_BIT0: equ %00000001 ; MTST1 Bit 0
mMTST1_BIT1: equ %00000010 ; MTST1 Bit 1
mMTST1_BIT2: equ %00000100 ; MTST1 Bit 2
mMTST1_BIT3: equ %00001000 ; MTST1 Bit 3
mMTST1_BIT4: equ %00010000 ; MTST1 Bit 4
mMTST1_BIT5: equ %00100000 ; MTST1 Bit 5
mMTST1_BIT6: equ %01000000 ; MTST1 Bit 6
mMTST1_BIT7: equ %10000000 ; MTST1 Bit 7
;*** PARTIDH - Part ID Register High; 0x0000001A ***
PARTIDH: equ $0000001A ;*** PARTIDH - Part ID Register High; 0x0000001A ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PARTIDH_ID15: equ 0 ; Part ID Register Bit 15
PARTIDH_ID14: equ 1 ; Part ID Register Bit 14
PARTIDH_ID13: equ 2 ; Part ID Register Bit 13
PARTIDH_ID12: equ 3 ; Part ID Register Bit 12
PARTIDH_ID11: equ 4 ; Part ID Register Bit 11
PARTIDH_ID10: equ 5 ; Part ID Register Bit 10
PARTIDH_ID9: equ 6 ; Part ID Register Bit 9
PARTIDH_ID8: equ 7 ; Part ID Register Bit 8
; bit position masks
mPARTIDH_ID15: equ %00000001 ; Part ID Register Bit 15
mPARTIDH_ID14: equ %00000010 ; Part ID Register Bit 14
mPARTIDH_ID13: equ %00000100 ; Part ID Register Bit 13
mPARTIDH_ID12: equ %00001000 ; Part ID Register Bit 12
mPARTIDH_ID11: equ %00010000 ; Part ID Register Bit 11
mPARTIDH_ID10: equ %00100000 ; Part ID Register Bit 10
mPARTIDH_ID9: equ %01000000 ; Part ID Register Bit 9
mPARTIDH_ID8: equ %10000000 ; Part ID Register Bit 8
;*** PARTIDL - Part ID Register Low; 0x0000001B ***
PARTIDL: equ $0000001B ;*** PARTIDL - Part ID Register Low; 0x0000001B ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PARTIDL_ID0: equ 0 ; Part ID Register Bit 0
PARTIDL_ID1: equ 1 ; Part ID Register Bit 1
PARTIDL_ID2: equ 2 ; Part ID Register Bit 2
PARTIDL_ID3: equ 3 ; Part ID Register Bit 3
PARTIDL_ID4: equ 4 ; Part ID Register Bit 4
PARTIDL_ID5: equ 5 ; Part ID Register Bit 5
PARTIDL_ID6: equ 6 ; Part ID Register Bit 6
PARTIDL_ID7: equ 7 ; Part ID Register Bit 7
; bit position masks
mPARTIDL_ID0: equ %00000001 ; Part ID Register Bit 0
mPARTIDL_ID1: equ %00000010 ; Part ID Register Bit 1
mPARTIDL_ID2: equ %00000100 ; Part ID Register Bit 2
mPARTIDL_ID3: equ %00001000 ; Part ID Register Bit 3
mPARTIDL_ID4: equ %00010000 ; Part ID Register Bit 4
mPARTIDL_ID5: equ %00100000 ; Part ID Register Bit 5
mPARTIDL_ID6: equ %01000000 ; Part ID Register Bit 6
mPARTIDL_ID7: equ %10000000 ; Part ID Register Bit 7
;*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***
MEMSIZ0: equ $0000001C ;*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
MEMSIZ0_ram_sw0: equ 0 ; Allocated RAM Memory Space Bit 0
MEMSIZ0_ram_sw1: equ 1 ; Allocated RAM Memory Space Bit 1
MEMSIZ0_ram_sw2: equ 2 ; Allocated RAM Memory Space Bit 2
MEMSIZ0_eep_sw0: equ 4 ; Allocated EEPROM Memory Space Bit 0
MEMSIZ0_eep_sw1: equ 5 ; Allocated EEPROM Memory Space Bit 1
MEMSIZ0_reg_sw0: equ 7 ; Allocated System Register Space
; bit position masks
mMEMSIZ0_ram_sw0: equ %00000001 ; Allocated RAM Memory Space Bit 0
mMEMSIZ0_ram_sw1: equ %00000010 ; Allocated RAM Memory Space Bit 1
mMEMSIZ0_ram_sw2: equ %00000100 ; Allocated RAM Memory Space Bit 2
mMEMSIZ0_eep_sw0: equ %00010000 ; Allocated EEPROM Memory Space Bit 0
mMEMSIZ0_eep_sw1: equ %00100000 ; Allocated EEPROM Memory Space Bit 1
mMEMSIZ0_reg_sw0: equ %10000000 ; Allocated System Register Space
;*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***
MEMSIZ1: equ $0000001D ;*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
MEMSIZ1_pag_sw0: equ 0 ; Allocated Off-Chip Memory Options Bit 0
MEMSIZ1_pag_sw1: equ 1 ; Allocated Off-Chip Memory Options Bit 1
MEMSIZ1_rom_sw0: equ 6 ; Allocated Flash EEPROM/ROM Physical Memory Space Bit 0
MEMSIZ1_rom_sw1: equ 7 ; Allocated Flash EEPROM/ROM Physical Memory Space Bit 1
; bit position masks
mMEMSIZ1_pag_sw0: equ %00000001 ; Allocated Off-Chip Memory Options Bit 0
mMEMSIZ1_pag_sw1: equ %00000010 ; Allocated Off-Chip Memory Options Bit 1
mMEMSIZ1_rom_sw0: equ %01000000 ; Allocated Flash EEPROM/ROM Physical Memory Space Bit 0
mMEMSIZ1_rom_sw1: equ %10000000 ; Allocated Flash EEPROM/ROM Physical Memory Space Bit 1
;*** INTCR - Interrupt Control Register; 0x0000001E ***
INTCR: equ $0000001E ;*** INTCR - Interrupt Control Register; 0x0000001E ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
INTCR_IRQEN: equ 6 ; External IRQ Enable
INTCR_IRQE: equ 7 ; IRQ Select Edge Sensitive Only
; bit position masks
mINTCR_IRQEN: equ %01000000 ; External IRQ Enable
mINTCR_IRQE: equ %10000000 ; IRQ Select Edge Sensitive Only
;*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***
HPRIO: equ $0000001F ;*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
HPRIO_PSEL1: equ 1 ; Highest Priority I Interrupt Bit 1
HPRIO_PSEL2: equ 2 ; Highest Priority I Interrupt Bit 2
HPRIO_PSEL3: equ 3 ; Highest Priority I Interrupt Bit 3
HPRIO_PSEL4: equ 4 ; Highest Priority I Interrupt Bit 4
HPRIO_PSEL5: equ 5 ; Highest Priority I Interrupt Bit 5
HPRIO_PSEL6: equ 6 ; Highest Priority I Interrupt Bit 6
HPRIO_PSEL7: equ 7 ; Highest Priority I Interrupt Bit 7
; bit position masks
mHPRIO_PSEL1: equ %00000010 ; Highest Priority I Interrupt Bit 1
mHPRIO_PSEL2: equ %00000100 ; Highest Priority I Interrupt Bit 2
mHPRIO_PSEL3: equ %00001000 ; Highest Priority I Interrupt Bit 3
mHPRIO_PSEL4: equ %00010000 ; Highest Priority I Interrupt Bit 4
mHPRIO_PSEL5: equ %00100000 ; Highest Priority I Interrupt Bit 5
mHPRIO_PSEL6: equ %01000000 ; Highest Priority I Interrupt Bit 6
mHPRIO_PSEL7: equ %10000000 ; Highest Priority I Interrupt Bit 7
;*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***
BKPCT0: equ $00000028 ;*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
BKPCT0_BKTAG: equ 4 ; Breakpoint on Tag
BKPCT0_BKBDM: equ 5 ; Breakpoint Background Debug Mode Enable
BKPCT0_BKFULL: equ 6 ; Full Breakpoint Mode Enable
BKPCT0_BKEN: equ 7 ; Breakpoint Enable
; bit position masks
mBKPCT0_BKTAG: equ %00010000 ; Breakpoint on Tag
mBKPCT0_BKBDM: equ %00100000 ; Breakpoint Background Debug Mode Enable
mBKPCT0_BKFULL: equ %01000000 ; Full Breakpoint Mode Enable
mBKPCT0_BKEN: equ %10000000 ; Breakpoint Enable
;*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***
BKPCT1: equ $00000029 ;*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
BKPCT1_BK1RW: equ 0 ; R/W Compare Value 1
BKPCT1_BK1RWE: equ 1 ; R/W Compare Enable 1
BKPCT1_BK0RW: equ 2 ; R/W Compare Value 0
BKPCT1_BK0RWE: equ 3 ; R/W Compare Enable 0
BKPCT1_BK1MBL: equ 4 ; Breakpoint Mask Low Byte for Second Address
BKPCT1_BK1MBH: equ 5 ; Breakpoint Mask High Byte for Second Address
BKPCT1_BK0MBL: equ 6 ; Breakpoint Mask Low Byte for First Address
BKPCT1_BK0MBH: equ 7 ; Breakpoint Mask High Byte for First Address
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