📄 main.dbg
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PEAR_NOACCE: equ 7 ; CPU No Access Output Enable
; bit position masks
mPEAR_RDWE: equ %00000100 ; Read / Write Enable
mPEAR_LSTRE: equ %00001000 ; Low Strobe (LSTRB) Enable
mPEAR_NECLK: equ %00010000 ; No External E Clock
mPEAR_PIPOE: equ %00100000 ; Pipe Status Signal Output Enable
mPEAR_NOACCE: equ %10000000 ; CPU No Access Output Enable
;*** MODE - Mode Register; 0x0000000B ***
MODE: equ $0000000B ;*** MODE - Mode Register; 0x0000000B ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
MODE_EME: equ 0 ; Emulate Port E
MODE_EMK: equ 1 ; Emulate Port K
MODE_IVIS: equ 3 ; Internal Visibility
MODE_MODA: equ 5 ; Mode Select Bit A
MODE_MODB: equ 6 ; Mode Select Bit B
MODE_MODC: equ 7 ; Mode Select Bit C
; bit position masks
mMODE_EME: equ %00000001 ; Emulate Port E
mMODE_EMK: equ %00000010 ; Emulate Port K
mMODE_IVIS: equ %00001000 ; Internal Visibility
mMODE_MODA: equ %00100000 ; Mode Select Bit A
mMODE_MODB: equ %01000000 ; Mode Select Bit B
mMODE_MODC: equ %10000000 ; Mode Select Bit C
;*** PUCR - Pull-Up Control Register; 0x0000000C ***
PUCR: equ $0000000C ;*** PUCR - Pull-Up Control Register; 0x0000000C ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PUCR_PUPAE: equ 0 ; Pull-Up Port A Enable
PUCR_PUPBE: equ 1 ; Pull-Up Port B Enable
PUCR_PUPEE: equ 4 ; Pull-Up Port E Enable
PUCR_PUPKE: equ 7 ; Pull-Up Port K Enable
; bit position masks
mPUCR_PUPAE: equ %00000001 ; Pull-Up Port A Enable
mPUCR_PUPBE: equ %00000010 ; Pull-Up Port B Enable
mPUCR_PUPEE: equ %00010000 ; Pull-Up Port E Enable
mPUCR_PUPKE: equ %10000000 ; Pull-Up Port K Enable
;*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***
RDRIV: equ $0000000D ;*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
RDRIV_RDPA: equ 0 ; Reduced Drive of Port A
RDRIV_RDPB: equ 1 ; Reduced Drive of Port B
RDRIV_RDPE: equ 4 ; Reduced Drive of Port E
RDRIV_RDPK: equ 7 ; Reduced Drive of Port K
; bit position masks
mRDRIV_RDPA: equ %00000001 ; Reduced Drive of Port A
mRDRIV_RDPB: equ %00000010 ; Reduced Drive of Port B
mRDRIV_RDPE: equ %00010000 ; Reduced Drive of Port E
mRDRIV_RDPK: equ %10000000 ; Reduced Drive of Port K
;*** EBICTL - External Bus Interface Control; 0x0000000E ***
EBICTL: equ $0000000E ;*** EBICTL - External Bus Interface Control; 0x0000000E ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
EBICTL_ESTR: equ 0 ; E Stretches
; bit position masks
mEBICTL_ESTR: equ %00000001 ; E Stretches
;*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***
INITRM: equ $00000010 ;*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
INITRM_RAMHAL: equ 0 ; Internal RAM map alignment
INITRM_RAM11: equ 3 ; Internal RAM map position Bit 11
INITRM_RAM12: equ 4 ; Internal RAM map position Bit 12
INITRM_RAM13: equ 5 ; Internal RAM map position Bit 13
INITRM_RAM14: equ 6 ; Internal RAM map position Bit 14
INITRM_RAM15: equ 7 ; Internal RAM map position Bit 15
; bit position masks
mINITRM_RAMHAL: equ %00000001 ; Internal RAM map alignment
mINITRM_RAM11: equ %00001000 ; Internal RAM map position Bit 11
mINITRM_RAM12: equ %00010000 ; Internal RAM map position Bit 12
mINITRM_RAM13: equ %00100000 ; Internal RAM map position Bit 13
mINITRM_RAM14: equ %01000000 ; Internal RAM map position Bit 14
mINITRM_RAM15: equ %10000000 ; Internal RAM map position Bit 15
;*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***
INITRG: equ $00000011 ;*** INITRG - Initialization of Internal Register Position Register; 0x00000011 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
INITRG_REG11: equ 3 ; Internal register map position REG11
INITRG_REG12: equ 4 ; Internal register map position REG12
INITRG_REG13: equ 5 ; Internal register map position REG13
INITRG_REG14: equ 6 ; Internal register map position REG14
; bit position masks
mINITRG_REG11: equ %00001000 ; Internal register map position REG11
mINITRG_REG12: equ %00010000 ; Internal register map position REG12
mINITRG_REG13: equ %00100000 ; Internal register map position REG13
mINITRG_REG14: equ %01000000 ; Internal register map position REG14
;*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***
INITEE: equ $00000012 ;*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
INITEE_EEON: equ 0 ; Internal EEPROM On
INITEE_EE12: equ 4 ; Internal EEPROM map position Bit 12
INITEE_EE13: equ 5 ; Internal EEPROM map position Bit 13
INITEE_EE14: equ 6 ; Internal EEPROM map position Bit 14
INITEE_EE15: equ 7 ; Internal EEPROM map position Bit 15
; bit position masks
mINITEE_EEON: equ %00000001 ; Internal EEPROM On
mINITEE_EE12: equ %00010000 ; Internal EEPROM map position Bit 12
mINITEE_EE13: equ %00100000 ; Internal EEPROM map position Bit 13
mINITEE_EE14: equ %01000000 ; Internal EEPROM map position Bit 14
mINITEE_EE15: equ %10000000 ; Internal EEPROM map position Bit 15
;*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***
MISC: equ $00000013 ;*** MISC - Miscellaneous Mapping Control Register; 0x00000013 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
MISC_ROMON: equ 0 ; Enable Flash EEPROM
MISC_ROMHM: equ 1 ; Flash EEPROM only in second half of memory map
MISC_EXSTR0: equ 2 ; External Access Stretch Bit 0
MISC_EXSTR1: equ 3 ; External Access Stretch Bit 1
; bit position masks
mMISC_ROMON: equ %00000001 ; Enable Flash EEPROM
mMISC_ROMHM: equ %00000010 ; Flash EEPROM only in second half of memory map
mMISC_EXSTR0: equ %00000100 ; External Access Stretch Bit 0
mMISC_EXSTR1: equ %00001000 ; External Access Stretch Bit 1
;*** MTST0 - MTST0; 0x00000014 ***
MTST0: equ $00000014 ;*** MTST0 - MTST0; 0x00000014 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
MTST0_BIT0: equ 0 ; MTST0 Bit 0
MTST0_BIT1: equ 1 ; MTST0 Bit 1
MTST0_BIT2: equ 2 ; MTST0 Bit 2
MTST0_BIT3: equ 3 ; MTST0 Bit 3
MTST0_BIT4: equ 4 ; MTST0 Bit 4
MTST0_BIT5: equ 5 ; MTST0 Bit 5
MTST0_BIT6: equ 6 ; MTST0 Bit 6
MTST0_BIT7: equ 7 ; MTST0 Bit 7
; bit position masks
mMTST0_BIT0: equ %00000001 ; MTST0 Bit 0
mMTST0_BIT1: equ %00000010 ; MTST0 Bit 1
mMTST0_BIT2: equ %00000100 ; MTST0 Bit 2
mMTST0_BIT3: equ %00001000 ; MTST0 Bit 3
mMTST0_BIT4: equ %00010000 ; MTST0 Bit 4
mMTST0_BIT5: equ %00100000 ; MTST0 Bit 5
mMTST0_BIT6: equ %01000000 ; MTST0 Bit 6
mMTST0_BIT7: equ %10000000 ; MTST0 Bit 7
;*** ITCR - Interrupt Test Control Register; 0x00000015 ***
ITCR: equ $00000015 ;*** ITCR - Interrupt Test Control Register; 0x00000015 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
ITCR_ADR0: equ 0 ; Test register select Bit 0
ITCR_ADR1: equ 1 ; Test register select Bit 1
ITCR_ADR2: equ 2 ; Test register select Bit 2
ITCR_ADR3: equ 3 ; Test register select Bit 3
ITCR_WRTINT: equ 4 ; Write to the Interrupt Test Registers
; bit position masks
mITCR_ADR0: equ %00000001 ; Test register select Bit 0
mITCR_ADR1: equ %00000010 ; Test register select Bit 1
mITCR_ADR2: equ %00000100 ; Test register select Bit 2
mITCR_ADR3: equ %00001000 ; Test register select Bit 3
mITCR_WRTINT: equ %00010000 ; Write to the Interrupt Test Registers
;*** ITEST - Interrupt Test Register; 0x00000016 ***
ITEST: equ $00000016 ;*** ITEST - Interrupt Test Register; 0x00000016 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
ITEST_INT0: equ 0 ; Interrupt Test Register Bit 0
ITEST_INT2: equ 1 ; Interrupt Test Register Bit 1
ITEST_INT4: equ 2 ; Interrupt Test Register Bit 2
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