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📄 main.dbg

📁 base on the mc9sdg128b LCD display
💻 DBG
📖 第 1 页 / 共 5 页
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PORTA_BIT5:         equ    5                                         ; Port A Bit5, ADDR13, DATA13, DATA5
PORTA_BIT6:         equ    6                                         ; Port A Bit6, ADDR14, DATA14, DATA6
PORTA_BIT7:         equ    7                                         ; Port A Bit7, ADDR15, DATA15, DATA7
; bit position masks
mPORTA_BIT0:        equ    %00000001                                ; Port A Bit0, ADDR8, DATA8, DATA0
mPORTA_BIT1:        equ    %00000010                                ; Port A Bit1, ADDR9, DATA9 DATA1
mPORTA_BIT2:        equ    %00000100                                ; Port A Bit2, ADDR10, DATA10, DATA2
mPORTA_BIT3:        equ    %00001000                                ; Port A Bit3, ADDR11, DATA11, DATA3
mPORTA_BIT4:        equ    %00010000                                ; Port A Bit4, ADDR12, DATA12, DATA4
mPORTA_BIT5:        equ    %00100000                                ; Port A Bit5, ADDR13, DATA13, DATA5
mPORTA_BIT6:        equ    %01000000                                ; Port A Bit6, ADDR14, DATA14, DATA6
mPORTA_BIT7:        equ    %10000000                                ; Port A Bit7, ADDR15, DATA15, DATA7


;*** PORTB - Port B Register; 0x00000001 ***
PORTB:              equ    $00000001                                ;*** PORTB - Port B Register; 0x00000001 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PORTB_BIT0:         equ    0                                         ; Port B Bit 0, ADDR0, DATA0
PORTB_BIT1:         equ    1                                         ; Port B Bit1, ADDR1, DATA1
PORTB_BIT2:         equ    2                                         ; Port B Bit2, ADDR2, DATA2
PORTB_BIT3:         equ    3                                         ; Port B Bit3, ADDR3, DATA3
PORTB_BIT4:         equ    4                                         ; Port B Bit4, ADDR4, DATA4
PORTB_BIT5:         equ    5                                         ; Port B Bit5, ADDR5, DATA5
PORTB_BIT6:         equ    6                                         ; Port B Bit6, ADDR6, DATA6
PORTB_BIT7:         equ    7                                         ; Port B Bit7, ADDR7, DATA7
; bit position masks
mPORTB_BIT0:        equ    %00000001                                ; Port B Bit 0, ADDR0, DATA0
mPORTB_BIT1:        equ    %00000010                                ; Port B Bit1, ADDR1, DATA1
mPORTB_BIT2:        equ    %00000100                                ; Port B Bit2, ADDR2, DATA2
mPORTB_BIT3:        equ    %00001000                                ; Port B Bit3, ADDR3, DATA3
mPORTB_BIT4:        equ    %00010000                                ; Port B Bit4, ADDR4, DATA4
mPORTB_BIT5:        equ    %00100000                                ; Port B Bit5, ADDR5, DATA5
mPORTB_BIT6:        equ    %01000000                                ; Port B Bit6, ADDR6, DATA6
mPORTB_BIT7:        equ    %10000000                                ; Port B Bit7, ADDR7, DATA7


;*** DDRAB - Port AB Data Direction Register; 0x00000002 ***
DDRAB:              equ    $00000002                                ;*** DDRAB - Port AB Data Direction Register; 0x00000002 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
DDRAB_BIT0:         equ    0                                         ; Data Direction Port B Bit 0
DDRAB_BIT1:         equ    1                                         ; Data Direction Port B Bit 1
DDRAB_BIT2:         equ    2                                         ; Data Direction Port B Bit 2
DDRAB_BIT3:         equ    3                                         ; Data Direction Port B Bit 3
DDRAB_BIT4:         equ    4                                         ; Data Direction Port B Bit 4
DDRAB_BIT5:         equ    5                                         ; Data Direction Port B Bit 5
DDRAB_BIT6:         equ    6                                         ; Data Direction Port B Bit 6
DDRAB_BIT7:         equ    7                                         ; Data Direction Port B Bit 7
DDRAB_BIT8:         equ    8                                         ; Data Direction Port A Bit 8
DDRAB_BIT9:         equ    9                                         ; Data Direction Port A Bit 9
DDRAB_BIT10:        equ    10                                        ; Data Direction Port A Bit 10
DDRAB_BIT11:        equ    11                                        ; Data Direction Port A Bit 11
DDRAB_BIT12:        equ    12                                        ; Data Direction Port A Bit 12
DDRAB_BIT13:        equ    13                                        ; Data Direction Port A Bit 13
DDRAB_BIT14:        equ    14                                        ; Data Direction Port A Bit 14
DDRAB_BIT15:        equ    15                                        ; Data Direction Port A Bit 15
; bit position masks
mDDRAB_BIT0:        equ    %00000001                                ; Data Direction Port B Bit 0
mDDRAB_BIT1:        equ    %00000010                                ; Data Direction Port B Bit 1
mDDRAB_BIT2:        equ    %00000100                                ; Data Direction Port B Bit 2
mDDRAB_BIT3:        equ    %00001000                                ; Data Direction Port B Bit 3
mDDRAB_BIT4:        equ    %00010000                                ; Data Direction Port B Bit 4
mDDRAB_BIT5:        equ    %00100000                                ; Data Direction Port B Bit 5
mDDRAB_BIT6:        equ    %01000000                                ; Data Direction Port B Bit 6
mDDRAB_BIT7:        equ    %10000000                                ; Data Direction Port B Bit 7
mDDRAB_BIT8:        equ    %100000000                               ; Data Direction Port A Bit 8
mDDRAB_BIT9:        equ    %1000000000                              ; Data Direction Port A Bit 9
mDDRAB_BIT10:       equ    %10000000000                             ; Data Direction Port A Bit 10
mDDRAB_BIT11:       equ    %100000000000                            ; Data Direction Port A Bit 11
mDDRAB_BIT12:       equ    %1000000000000                           ; Data Direction Port A Bit 12
mDDRAB_BIT13:       equ    %10000000000000                          ; Data Direction Port A Bit 13
mDDRAB_BIT14:       equ    %100000000000000                         ; Data Direction Port A Bit 14
mDDRAB_BIT15:       equ    %1000000000000000                        ; Data Direction Port A Bit 15


;*** DDRA - Port A Data Direction Register; 0x00000002 ***
DDRA:               equ    $00000002                                ;*** DDRA - Port A Data Direction Register; 0x00000002 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
DDRA_BIT0:          equ    0                                         ; Data Direction Port A Bit 0
DDRA_BIT1:          equ    1                                         ; Data Direction Port A Bit 1
DDRA_BIT2:          equ    2                                         ; Data Direction Port A Bit 2
DDRA_BIT3:          equ    3                                         ; Data Direction Port A Bit 3
DDRA_BIT4:          equ    4                                         ; Data Direction Port A Bit 4
DDRA_BIT5:          equ    5                                         ; Data Direction Port A Bit 5
DDRA_BIT6:          equ    6                                         ; Data Direction Port A Bit 6
DDRA_BIT7:          equ    7                                         ; Data Direction Port A Bit 7
; bit position masks
mDDRA_BIT0:         equ    %00000001                                ; Data Direction Port A Bit 0
mDDRA_BIT1:         equ    %00000010                                ; Data Direction Port A Bit 1
mDDRA_BIT2:         equ    %00000100                                ; Data Direction Port A Bit 2
mDDRA_BIT3:         equ    %00001000                                ; Data Direction Port A Bit 3
mDDRA_BIT4:         equ    %00010000                                ; Data Direction Port A Bit 4
mDDRA_BIT5:         equ    %00100000                                ; Data Direction Port A Bit 5
mDDRA_BIT6:         equ    %01000000                                ; Data Direction Port A Bit 6
mDDRA_BIT7:         equ    %10000000                                ; Data Direction Port A Bit 7


;*** DDRB - Port B Data Direction Register; 0x00000003 ***
DDRB:               equ    $00000003                                ;*** DDRB - Port B Data Direction Register; 0x00000003 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
DDRB_BIT0:          equ    0                                         ; Data Direction Port B Bit 0
DDRB_BIT1:          equ    1                                         ; Data Direction Port B Bit 1
DDRB_BIT2:          equ    2                                         ; Data Direction Port B Bit 2
DDRB_BIT3:          equ    3                                         ; Data Direction Port B Bit 3
DDRB_BIT4:          equ    4                                         ; Data Direction Port B Bit 4
DDRB_BIT5:          equ    5                                         ; Data Direction Port B Bit 5
DDRB_BIT6:          equ    6                                         ; Data Direction Port B Bit 6
DDRB_BIT7:          equ    7                                         ; Data Direction Port B Bit 7
; bit position masks
mDDRB_BIT0:         equ    %00000001                                ; Data Direction Port B Bit 0
mDDRB_BIT1:         equ    %00000010                                ; Data Direction Port B Bit 1
mDDRB_BIT2:         equ    %00000100                                ; Data Direction Port B Bit 2
mDDRB_BIT3:         equ    %00001000                                ; Data Direction Port B Bit 3
mDDRB_BIT4:         equ    %00010000                                ; Data Direction Port B Bit 4
mDDRB_BIT5:         equ    %00100000                                ; Data Direction Port B Bit 5
mDDRB_BIT6:         equ    %01000000                                ; Data Direction Port B Bit 6
mDDRB_BIT7:         equ    %10000000                                ; Data Direction Port B Bit 7


;*** PORTE - Port E Register; 0x00000008 ***
PORTE:              equ    $00000008                                ;*** PORTE - Port E Register; 0x00000008 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PORTE_BIT0:         equ    0                                         ; Port E Bit 0, XIRQ
PORTE_BIT1:         equ    1                                         ; Port E Bit 1, IRQ
PORTE_BIT2:         equ    2                                         ; Port E Bit 2, R/W
PORTE_BIT3:         equ    3                                         ; Port E Bit 3, LSTRB, TAGLO
PORTE_BIT4:         equ    4                                         ; Port E Bit 4, ECLK
PORTE_BIT5:         equ    5                                         ; Port E Bit 5, MODA, IPIPE0, RCRTO
PORTE_BIT6:         equ    6                                         ; Port E Bit 6, MODB, IPIPE1, SCGTO
PORTE_BIT7:         equ    7                                         ; Port E Bit 7, XCLKS, NOACC
; bit position masks
mPORTE_BIT0:        equ    %00000001                                ; Port E Bit 0, XIRQ
mPORTE_BIT1:        equ    %00000010                                ; Port E Bit 1, IRQ
mPORTE_BIT2:        equ    %00000100                                ; Port E Bit 2, R/W
mPORTE_BIT3:        equ    %00001000                                ; Port E Bit 3, LSTRB, TAGLO
mPORTE_BIT4:        equ    %00010000                                ; Port E Bit 4, ECLK
mPORTE_BIT5:        equ    %00100000                                ; Port E Bit 5, MODA, IPIPE0, RCRTO
mPORTE_BIT6:        equ    %01000000                                ; Port E Bit 6, MODB, IPIPE1, SCGTO
mPORTE_BIT7:        equ    %10000000                                ; Port E Bit 7, XCLKS, NOACC


;*** DDRE - Port E Data Direction Register; 0x00000009 ***
DDRE:               equ    $00000009                                ;*** DDRE - Port E Data Direction Register; 0x00000009 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
DDRE_BIT0:          equ    0                                         ; Data Direction Port A Bit 0
DDRE_BIT1:          equ    1                                         ; Data Direction Port A Bit 1
DDRE_BIT2:          equ    2                                         ; Data Direction Port A Bit 2
DDRE_BIT3:          equ    3                                         ; Data Direction Port A Bit 3
DDRE_BIT4:          equ    4                                         ; Data Direction Port A Bit 4
DDRE_BIT5:          equ    5                                         ; Data Direction Port A Bit 5
DDRE_BIT6:          equ    6                                         ; Data Direction Port A Bit 6
DDRE_BIT7:          equ    7                                         ; Data Direction Port A Bit 7
; bit position masks
mDDRE_BIT0:         equ    %00000001                                ; Data Direction Port A Bit 0
mDDRE_BIT1:         equ    %00000010                                ; Data Direction Port A Bit 1
mDDRE_BIT2:         equ    %00000100                                ; Data Direction Port A Bit 2
mDDRE_BIT3:         equ    %00001000                                ; Data Direction Port A Bit 3
mDDRE_BIT4:         equ    %00010000                                ; Data Direction Port A Bit 4
mDDRE_BIT5:         equ    %00100000                                ; Data Direction Port A Bit 5
mDDRE_BIT6:         equ    %01000000                                ; Data Direction Port A Bit 6
mDDRE_BIT7:         equ    %10000000                                ; Data Direction Port A Bit 7


;*** PEAR - Port E Assignment Register; 0x0000000A ***
PEAR:               equ    $0000000A                                ;*** PEAR - Port E Assignment Register; 0x0000000A ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PEAR_RDWE:          equ    2                                         ; Read / Write Enable
PEAR_LSTRE:         equ    3                                         ; Low Strobe (LSTRB) Enable
PEAR_NECLK:         equ    4                                         ; No External E Clock
PEAR_PIPOE:         equ    5                                         ; Pipe Status Signal Output Enable

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