📄 fft_system.ptf
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MASTER tightly_coupled_data_master_2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Is_Readable = "1";
Is_Writeable = "1";
Address_Group = "0";
DBS_Big_Endian = "0";
}
}
MASTER tightly_coupled_data_master_3
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Is_Readable = "1";
Is_Writeable = "1";
Address_Group = "0";
DBS_Big_Endian = "0";
}
}
MASTER tightly_coupled_instruction_master_0
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
DBS_Big_Endian = "0";
}
}
MASTER tightly_coupled_instruction_master_1
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Address_Group = "0";
DBS_Big_Endian = "0";
}
}
MASTER tightly_coupled_instruction_master_2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Address_Group = "0";
DBS_Big_Endian = "0";
}
}
MASTER tightly_coupled_instruction_master_3
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
Address_Group = "0";
DBS_Big_Endian = "0";
}
}
SOFTWARE_COMPONENT altera_nios2_test
{
class = "altera_nios2_test";
class_version = "2.0";
WIZARD_SCRIPT_ARGUMENTS
{
CONSTANTS
{
CONSTANT debug_on
{
value = "0";
comment = "Enable debug features";
}
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "0";
}
}
}
MODULE sdram
{
class = "altera_avalon_new_sdram_controller";
class_version = "6.0";
iss_model_name = "altera_memory";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Maximum_Pending_Read_Transactions = "7";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Is_Memory_Device = "1";
Address_Width = "22";
Data_Width = "32";
Simulation_Num_Lanes = "1";
Base_Address = "0x00000000";
MASTERED_BY cpu/instruction_master
{
priority = "8";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Is_Base_Locked = "0";
Address_Group = "0";
}
PORT_WIRING
{
PORT az_addr
{
direction = "input";
type = "address";
width = "22";
Is_Enabled = "1";
}
PORT az_be_n
{
direction = "input";
type = "byteenable_n";
width = "4";
Is_Enabled = "1";
}
PORT az_cs
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT az_data
{
direction = "input";
type = "writedata";
width = "32";
Is_Enabled = "1";
}
PORT az_rd_n
{
direction = "input";
type = "read_n";
width = "1";
Is_Enabled = "1";
}
PORT az_wr_n
{
direction = "input";
type = "write_n";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT za_data
{
direction = "output";
type = "readdata";
width = "32";
Is_Enabled = "1";
}
PORT za_valid
{
direction = "output";
type = "readdatavalid";
width = "1";
Is_Enabled = "1";
}
PORT za_waitrequest
{
direction = "output";
type = "waitrequest";
width = "1";
Is_Enabled = "1";
}
PORT zs_addr
{
direction = "output";
width = "12";
Is_Enabled = "1";
is_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U57.25,U57.26,U57.27,U57.60,U57.61,U57.62,U57.63,U57.64,U57.65,U57.66,U57.24,U57.21";
pin_assignment = "AE4,W12,AC11,W10,AA11,AC10,AB11,AC8,AB10,V11,Y11,AB7";
}
originally_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60_es
{
component_pin = "U57.25,U57.26,U57.27,U57.60,U57.61,U57.62,U57.63,U57.64,U57.65,U57.66,U57.24,U57.21";
pin_assignment = "AD4,AD3,AD5,W9,W10,AB10,AF5,AE5,AC6,AF6,AA10,Y9";
}
}
PORT zs_ba
{
direction = "output";
width = "2";
Is_Enabled = "1";
is_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U57.22,U57.23";
pin_assignment = "AG19,AF19";
}
originally_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60_es
{
component_pin = "U57.22,U57.23";
pin_assignment = "AE23,AD23";
}
}
PORT zs_cas_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
is_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U57.18";
pin_assignment = "AD18";
}
originally_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60_es
{
component_pin = "U57.18";
pin_assignment = "AE16";
}
}
PORT zs_cke
{
direction = "output";
width = "1";
Is_Enabled = "1";
is_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U57.67";
pin_assignment = "AE18";
}
originally_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60_es
{
component_pin = "U57.67";
pin_assignment = "AE20";
}
}
PORT zs_cs_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
is_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U57.20";
pin_assignment = "AG18";
}
originally_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60_es
{
component_pin = "U57.20";
pin_assignment = "AE19";
}
}
PORT zs_dq
{
direction = "inout";
width = "32";
Is_Enabled = "1";
is_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U57.2,U57.4,U57.5,U57.7,U57.8,U57.10,U57.11,U57.13,U57.74,U57.76,U57.77,U57.79,U57.80,U57.82,U57.83,U57.85,U57.31,U57.33,U57.34,U57.36,U57.37,U57.39,U57.40,U57.42,U57.45,U57.47,U57.48,U57.50,U57.51,U57.53,U57.54,U57.56";
pin_assignment = "AH4,AE5,AG3,AG5,AG4,AF4,AH5,AF5,AE6,AG6,AH6,AD6,AF7,AH7,AG7,AF6,AG8,AF8,AD8,AH9,AH8,AE9,AF9,AG9,AD10,AF10,AH10,AE10,AF11,AE11,AH11,AG11";
}
originally_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60_es
{
component_pin = "U57.2,U57.4,U57.5,U57.7,U57.8,U57.10,U57.11,U57.13,U57.74,U57.76,U57.77,U57.79,U57.80,U57.82,U57.83,U57.85,U57.31,U57.33,U57.34,U57.36,U57.37,U57.39,U57.40,U57.42,U57.45,U57.47,U57.48,U57.50,U57.51,U57.53,U57.54,U57.56";
pin_assignment = "W15,V14,AA16,AD16,AF17,AD17,AF18,AA17,V16,AB17,AF19,AD18,AD19,AF20,AC17,V17,AB18,AF21,AD20,AD21,AF22,AC18,W18,AB19,AD22,AE22,AF24,AE24,AB7,V10,AA8,AF3";
}
}
PORT zs_dqm
{
direction = "output";
width = "4";
Is_Enabled = "1";
is_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U57.16,U57.71,U57.28,U57.59";
pin_assignment = "AE14,Y13,AE7,AG10";
}
originally_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60_es
{
component_pin = "U57.16,U57.71,U57.28,U57.59";
pin_assignment = "AF7,AD7,AC7,AF8";
}
}
PORT zs_ras_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
is_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U57.19";
pin_assignment = "AH3";
}
originally_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60_es
{
component_pin = "U57.19";
pin_assignment = "AE17";
}
}
PORT zs_we_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
is_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U57.17";
pin_assignment = "AH19";
}
originally_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60_es
{
component_pin = "U57.17";
pin_assignment = "AE18";
}
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "sdram";
Disable_Simulation_Port_Wiring = "0";
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