fft_system.ptf

在cycloneII里实现对FFT的硬件加速

               format = "Logic";
            }
            SIGNAL p
            {
               name = "ddr_cs_n";
               radix = "hexadecimal";
               format = "Logic";
            }
            SIGNAL q
            {
               name = "ddr_a";
               radix = "hexadecimal";
               format = "Logic";
            }
            SIGNAL r
            {
               name = "ddr_ba";
               radix = "hexadecimal";
               format = "Logic";
            }
            SIGNAL s
            {
               name = "ddr_ras_n";
               radix = "hexadecimal";
               format = "Logic";
            }
            SIGNAL t
            {
               name = "ddr_cas_n";
               radix = "hexadecimal";
               format = "Logic";
            }
            SIGNAL u
            {
               name = "ddr_we_n";
               radix = "hexadecimal";
               format = "Logic";
            }
            SIGNAL v
            {
               name = "ddr_dm";
               radix = "hexadecimal";
               format = "Logic";
            }
            SIGNAL w
            {
               name = "ddr_dq";
               radix = "hexadecimal";
               format = "Logic";
            }
            SIGNAL x
            {
               name = "ddr_dqs";
               radix = "hexadecimal";
               format = "Logic";
            }
            SIGNAL y
            {
               name = "ddr_cke";
               radix = "hexadecimal";
               format = "Logic";
            }
         }
         PORT_WIRING 
         {
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT ddr_cs_n
            {
               Is_Enabled = "1";
               direction = "output";
               width = "1";
            }
            PORT ddr_cke
            {
               Is_Enabled = "1";
               direction = "output";
               width = "1";
            }
            PORT ddr_a
            {
               Is_Enabled = "1";
               direction = "output";
               width = "13";
            }
            PORT ddr_ba
            {
               Is_Enabled = "1";
               direction = "output";
               width = "2";
            }
            PORT ddr_ras_n
            {
               Is_Enabled = "1";
               direction = "output";
               width = "1";
            }
            PORT ddr_cas_n
            {
               Is_Enabled = "1";
               direction = "output";
               width = "1";
            }
            PORT ddr_we_n
            {
               Is_Enabled = "1";
               direction = "output";
               width = "1";
            }
            PORT ddr_dq
            {
               Is_Enabled = "1";
               direction = "inout";
               width = "16";
            }
            PORT ddr_dqs
            {
               Is_Enabled = "1";
               direction = "inout";
               width = "2";
            }
            PORT ddr_dm
            {
               Is_Enabled = "1";
               direction = "output";
               width = "2";
            }
         }
      }
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Address_Alignment = "dynamic";
            Address_Width = "23";
            Data_Width = "32";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Instantiate_In_System_Module = "1";
            Is_Enabled = "1";
            Is_Bus_Master = "0";
            Bus_Type = "avalon";
            Has_IRQ = "0";
            Has_Base_Address = "1";
            Maximum_Pending_Read_Transactions = "16";
            Setup_Time = "0";
            Hold_Time = "0";
            Is_Memory_Device = "1";
            Uses_Tri_State_Data_Bus = "0";
            Maximum_Burst_Size = "1";
            Linewrap_Bursts = "1";
            Interleave_Bursts = "0";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
            }
            Base_Address = "0x00000000";
            Address_Group = "0";
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "NC";
            }
            Is_Base_Locked = "0";
         }
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               direction = "input";
               width = "1";
            }
            PORT write_clk
            {
               type = "export";
               direction = "input";
               width = "1";
            }
            PORT clk
            {
               type = "clk";
               direction = "input";
               width = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               direction = "input";
               width = "1";
            }
            PORT write_clk
            {
               type = "export";
               direction = "input";
               width = "1";
            }
            PORT local_read_req
            {
               type = "read";
               direction = "input";
               width = "1";
            }
            PORT local_write_req
            {
               type = "write";
               direction = "input";
               width = "1";
            }
            PORT local_addr
            {
               type = "address";
               direction = "input";
               width = "23";
            }
            PORT local_wdata
            {
               type = "writedata";
               direction = "input";
               width = "32";
            }
            PORT local_be
            {
               type = "byteenable";
               direction = "input";
               width = "4";
            }
            PORT local_ready
            {
               type = "waitrequest_n";
               direction = "output";
               width = "1";
            }
            PORT local_rdata
            {
               type = "readdata";
               direction = "output";
               width = "32";
            }
            PORT local_rdata_valid
            {
               type = "readdatavalid";
               direction = "output";
               width = "1";
            }
            PORT clk_to_sdram
            {
               type = "export";
               direction = "output";
               width = "1";
            }
            PORT clk_to_sdram_n
            {
               type = "export";
               direction = "output";
               width = "1";
            }
            PORT ddr_cs_n
            {
               type = "export";
               direction = "output";
               width = "1";
            }
            PORT ddr_cke
            {
               type = "export";
               direction = "output";
               width = "1";
            }
            PORT ddr_a
            {
               type = "export";
               direction = "output";
               width = "13";
            }
            PORT ddr_ba
            {
               type = "export";
               direction = "output";
               width = "2";
            }
            PORT ddr_ras_n
            {
               type = "export";
               direction = "output";
               width = "1";
            }
            PORT ddr_cas_n
            {
               type = "export";
               direction = "output";
               width = "1";
            }
            PORT ddr_we_n
            {
               type = "export";
               direction = "output";
               width = "1";
            }
            PORT ddr_dq
            {
               type = "export";
               direction = "inout";
               width = "16";
            }
            PORT ddr_dqs
            {
               type = "export";
               direction = "inout";
               width = "2";
            }
            PORT ddr_dm
            {
               type = "export";
               direction = "output";
               width = "2";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         MEGACORE 
         {
            title = "DDR SDRAM Controller";
            version = "3.3.0";
            iptb_version = "v1.2.11 build48";
            format_version = "120";
            NETLIST_SECTION 
            {
               class = "altera.ipbu.flowbase.netlist.model.DDRSDRAMModel";
               active_core = "sdram_auk_ddr_sdram";
               STATIC_SECTION 
               {
                  PRIVATES 
                  {
                     NAMESPACE parameterization
                     {
                        PRIVATE use_mem
                        {
                           value = "1";
                           type = "BOOLEAN";
                           enable = "1";
                        }
                        PRIVATE gMEM_TYPE
                        {
                           value = "ddr_sdram";
                           type = "STRING";
                           enable = "1";
                        }
                        PRIVATE projectname
                        {
                           value = "2c35_fft_acceleration";
                           type = "STRING";
                           enable = "1";
                        }
                        PRIVATE new_wizard
                        {
                           value = "false";
                           type = "STRING";
                           enable = "1";
                        }
                        PRIVATE local_burst_length
                        {
                           value = "1";
                           type = "INTEGER";
                           enable = "1";
                        }
                        PRIVATE burst_length
                        {
                           value = "2";
                           type = "INTEGER";
                           enable = "1";
                        }
                        PRIVATE odt_setting
                        {
                           value = "Disabled";
                           type = "STRING";
                           enable = "0";
                        }
                        PRIVATE chip_selects_per_dimm
                        {
                           value = "1";
                           type = "INTEGER";
                           enable = "0";
                        }
                        PRIVATE mig_device
                        {
                           value = "NONE";
                           type = "STRING";
                           enable = "1";
                        }
                        PRIVATE mig_package
                        {
                           value = "NONE";
                           type = "STRING";
                           enable = "1";
                        }
                        PRIVATE mig_speed_grade
                        {
                           value = "NONE";
                           type = "STRING";
                           enable = "1";
                        }
                        PRIVATE mig_family
                        {
                           value = "NONE";
                           type = "STRING";
                           enable = "1";
                        }
                        PRIVATE mig_defaultByteGroups
                        {
                           value = "default_value";
                           type = "STRING";
                           enable = "1";
                        }
                        PRIVATE mig_ByteGroups
                        {
                           value = "default_value";
                           type = "STRING";
                           enable = "1";
                        }
                        PRIVATE ADVANCED
                        {
                           value = "0";
                           type = "BOOLEAN";
                           enable = "1";
                        }
                        PRIVATE include_x4_dm_pins
                        {
                           value = "1";
                           type = "BOOLEAN";
                           enable = "0";
                        }
                        PRIVATE chipselects
                        {
                           value = "1";