📄 disp_br2.h.bak
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4, N_INC, SPREAD_SPECTRUM_99, 0x00, //Disable Spread Spectrum
7, Y_INC, DPLL_CTRL_D0, 0x28,0x37,0x35,0x04, //DCLK = 100MHz
13, Y_INC, PLL1_CTRL_D6, 0xf2,0x11,0x00,0x7f,0x30,0x0a,0x04,0x3f,0xff,0x81,
// 4, N_INC, ADC_CTRL_E6, 0xb0,
4, N_INC, ADC_CTRL_E6, 0x40,
4, N_INC, DV_BKGD_STA_31, 0x60,
4, N_INC, ADC_FRAME_MODULE_EB, 0x06,
4, N_INC, TMDS_CORRECTION_FF, 0x00,
9, Y_INC, TMDS_OUTPUT_ENA_A0, 0x0f, 0xef,0x8b,0x26,0x35,0x2f,
0
};
unsigned char code RTD_DDC_TABLE[] =
{
5, Y_INC, DDC_ENABLE_FC, 0x00,0x00, // Disable the DDC channel of VGA
131, N_INC, DDC_ACCESS_P_FE, 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00,
0x4a,0x8b,0x00,0x00,0x01,0x01,0x01,0x01,
0x1e,0x0c,0x01,0x01,0x0e,0x24,0x1b,0x78,
0xe8,0x8a,0x01,0x9a,0x58,0x52,0x8b,0x28,
0x1e,0x50,0x54,0xff,0xff,0x80,0x61,0x40,
0x61,0x4f,0x61,0x59,0x71,0x4f,0x81,0x40,
0x81,0x59,0x81,0x99,0xa9,0x40,0x00,0x00,
0x00,0xfc,0x00,0x31,0x37,0x27,0x27,0x20,
0x4c,0x43,0x44,0x0a,0x20,0x20,0x20,0x20,
0x00,0x00,0x00,0xfc,0x00,0x4d,0x6f,0x6e,
0x69,0x74,0x6f,0x72,0x0a,0x20,0x20,0x20,
0x20,0x20,0x00,0x00,0x00,0xfd,0x00,0x2b,
0x55,0x14,0x5c,0x0e,0x00,0x0a,0x20,0x20,
0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xff,
0x00,0x30,0x30,0x30,0x30,0x30,0x31,0x0a,
0x20,0x20,0x20,0x20,0x20,0x20,0x00,0xbd,
4, N_INC, DDC_ENABLE_FC, 0x05, // Enable the DDC channel of VGA
#if(TMDS_ENABLE)
5, Y_INC, DDC_ENABLE_BC, 0x00,0x00, // Disable the DDC channel of DVI
131, N_INC, DDC_ACCESS_PORT_BE, 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00,
0x26,0xCD,0x68,0x46,0x00,0x00,0x00,0x00,
0x23,0x0c,0x01,0x03,0x81,0x24,0x1D,0x78,
0xeF,0x0D,0xC2,0xa0,0x57,0x47,0x98,0x27,
0x12,0x48,0x4F,0xBF,0xEF,0x00,0x81,0x80,
0x81,0x8F,0x61,0x40,0x61,0x59,0x45,0x40,
0x45,0x59,0x31,0x40,0x31,0x59,0xBC,0x34,
0x00,0x98,0x51,0x00,0x2A,0x40,0x10,0x90,
0x13,0x00,0x68,0x22,0x11,0x00,0x00,0x1e,
0x00,0x00,0x00,0xFF,0x00,0x30,0x0A,0x20,
0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
0x20,0x20,0x00,0x00,0x00,0xFC,0x00,0x41,
0x53,0x34,0x36,0x33,0x37,0x20,0x20,0x20,
0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xFD,
0x00,0x38,0x55,0x18,0x50,0x0E,0x00,0x0A,
0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x06,
4, N_INC, DDC_ENABLE_BC, 0x05, // Enable the DDC channel of DVI
#endif
0
};
unsigned char code RTD_IO_INI[] =
{
4, N_INC, TC_ADDR_PORT_95, 0x00,
//********************* RSDS_TYPE **********************
9, N_INC, TC_DATA_PORT_96, 0x00,0x22,0x22,0xe3,0x70,0x22,
//--------------------------------------------------------------------
// For RSDS TCON START
//--------------------------------------------------------------------
// 5, Y_INC, TC_ADDR_PORT_95, 0x10,0x0c, // FXDIO TCON1
// 5, Y_INC, TC_ADDR_PORT_95, 0x11,0x40,
// 5, Y_INC, TC_ADDR_PORT_95, 0x12,0x0c,
// 5, Y_INC, TC_ADDR_PORT_95, 0x13,0xa0,
// 5, Y_INC, TC_ADDR_PORT_95, 0x14,0x22,
// 5, Y_INC, TC_ADDR_PORT_95, 0x15,0xa1,
// 5, Y_INC, TC_ADDR_PORT_95, 0x16,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x30,0x0c, // FXDIO TCON5
5, Y_INC, TC_ADDR_PORT_95, 0x31,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x32,0x0c,
5, Y_INC, TC_ADDR_PORT_95, 0x33,0xa0,
5, Y_INC, TC_ADDR_PORT_95, 0x34,0x22,
5, Y_INC, TC_ADDR_PORT_95, 0x35,0xa1,
5, Y_INC, TC_ADDR_PORT_95, 0x36,0x80,
// 5, Y_INC, TC_ADDR_PORT_95, 0x30,0x0c, // XSTB TCON5
// 5, Y_INC, TC_ADDR_PORT_95, 0x31,0x40,
// 5, Y_INC, TC_ADDR_PORT_95, 0x32,0X0c,
// 5, Y_INC, TC_ADDR_PORT_95, 0x33,0x35,
// 5, Y_INC, TC_ADDR_PORT_95, 0x34,0x22,
// 5, Y_INC, TC_ADDR_PORT_95, 0x35,0xac,
// 5, Y_INC, TC_ADDR_PORT_95, 0x36,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x38,0x0c, // XSTB TCON6
5, Y_INC, TC_ADDR_PORT_95, 0x39,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x3a,0X0c,
5, Y_INC, TC_ADDR_PORT_95, 0x3b,0x35,
5, Y_INC, TC_ADDR_PORT_95, 0x3c,0x22,
5, Y_INC, TC_ADDR_PORT_95, 0x3d,0xac,
5, Y_INC, TC_ADDR_PORT_95, 0x3e,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x60,0x0c, // YOE TCON11
5, Y_INC, TC_ADDR_PORT_95, 0x61,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x62,0x0c,
5, Y_INC, TC_ADDR_PORT_95, 0x63,0x94,
5, Y_INC, TC_ADDR_PORT_95, 0x64,0x52,
5, Y_INC, TC_ADDR_PORT_95, 0x65,0x14,
5, Y_INC, TC_ADDR_PORT_95, 0x66,0x80,
// 5, Y_INC, TC_ADDR_PORT_95, 0x66,0xc0,
// 5, Y_INC, TC_ADDR_PORT_95, 0x08,0x0c, // BXDIO TCON0
// 5, Y_INC, TC_ADDR_PORT_95, 0x09,0x40,
// 5, Y_INC, TC_ADDR_PORT_95, 0x0a,0x0c,
// 5, Y_INC, TC_ADDR_PORT_95, 0x0b,0x9f,
// 5, Y_INC, TC_ADDR_PORT_95, 0x0c,0x22,
// 5, Y_INC, TC_ADDR_PORT_95, 0x0d,0xa9,
// 5, Y_INC, TC_ADDR_PORT_95, 0x0e,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x48,0x0c, // BXDIO TCON8
5, Y_INC, TC_ADDR_PORT_95, 0x49,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x4a,0x0c,
5, Y_INC, TC_ADDR_PORT_95, 0x4b,0x9f,
5, Y_INC, TC_ADDR_PORT_95, 0x4c,0x22,
5, Y_INC, TC_ADDR_PORT_95, 0x4d,0xa9,
5, Y_INC, TC_ADDR_PORT_95, 0x4e,0x80,
// 5, Y_INC, TC_ADDR_PORT_95, 0x48,0x0c, // YCLK TCON8
// 5, Y_INC, TC_ADDR_PORT_95, 0x49,0x40,
// 5, Y_INC, TC_ADDR_PORT_95, 0x4a,0X0c,
// 5, Y_INC, TC_ADDR_PORT_95, 0x4b,0xF4,
// 5, Y_INC, TC_ADDR_PORT_95, 0x4c,0x21,
// 5, Y_INC, TC_ADDR_PORT_95, 0x4d,0x94,
// 5, Y_INC, TC_ADDR_PORT_95, 0x4e,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x50,0x0c, // YCLK TCON9
5, Y_INC, TC_ADDR_PORT_95, 0x51,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x52,0X0c,
5, Y_INC, TC_ADDR_PORT_95, 0x53,0xF4,
5, Y_INC, TC_ADDR_PORT_95, 0x54,0x21,
5, Y_INC, TC_ADDR_PORT_95, 0x55,0x94,
5, Y_INC, TC_ADDR_PORT_95, 0x56,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x58,0x0c, // YDIO TCON10
5, Y_INC, TC_ADDR_PORT_95, 0x59,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x5a,0x0e,
5, Y_INC, TC_ADDR_PORT_95, 0x5b,0xd0,
5, Y_INC, TC_ADDR_PORT_95, 0x5c,0x33,
5, Y_INC, TC_ADDR_PORT_95, 0x5d,0xd7,
5, Y_INC, TC_ADDR_PORT_95, 0x5e,0x88,
/*
5, Y_INC, TC_ADDR_PORT_95, 0x70,0x0c, // YOE TCON13
5, Y_INC, TC_ADDR_PORT_95, 0x71,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x72,0x0c,
5, Y_INC, TC_ADDR_PORT_95, 0x73,0x94,
5, Y_INC, TC_ADDR_PORT_95, 0x74,0x52,
5, Y_INC, TC_ADDR_PORT_95, 0x75,0x14,
5, Y_INC, TC_ADDR_PORT_95, 0x76,0x80,
*/
/*
5, Y_INC, TC_ADDR_PORT_95, 0x50,0x0c, // BXDIO TCON9
5, Y_INC, TC_ADDR_PORT_95, 0x51,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x52,0x0c,
5, Y_INC, TC_ADDR_PORT_95, 0x53,0x9f,
5, Y_INC, TC_ADDR_PORT_95, 0x54,0x22,
5, Y_INC, TC_ADDR_PORT_95, 0x55,0xa9,
5, Y_INC, TC_ADDR_PORT_95, 0x56,0x80,
*/
/*
5, Y_INC, TC_ADDR_PORT_95, 0x60,0x0c, // YDIO TCON9
5, Y_INC, TC_ADDR_PORT_95, 0x61,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x62,0x0e,
5, Y_INC, TC_ADDR_PORT_95, 0x63,0xd0,
5, Y_INC, TC_ADDR_PORT_95, 0x64,0x33,
5, Y_INC, TC_ADDR_PORT_95, 0x65,0xd7,
5, Y_INC, TC_ADDR_PORT_95, 0x66,0x88,
*/
/*
5, Y_INC, TC_ADDR_PORT_95, 0x58,0x0c, // YCLK TCON5
5, Y_INC, TC_ADDR_PORT_95, 0x59,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x5a,0X0c,
5, Y_INC, TC_ADDR_PORT_95, 0x5b,0xF4,
5, Y_INC, TC_ADDR_PORT_95, 0x5c,0x21,
5, Y_INC, TC_ADDR_PORT_95, 0x5d,0x94,
5, Y_INC, TC_ADDR_PORT_95, 0x5e,0x80,
*/
#if(ANTI_FLICKER)
5, Y_INC, TC_ADDR_PORT_95, 0x38,0x0c, // POL TCON6
5, Y_INC, TC_ADDR_PORT_95, 0x39,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x3a,0x0E,
5, Y_INC, TC_ADDR_PORT_95, 0x3b,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x3c,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x3d,0x01,
5, Y_INC, TC_ADDR_PORT_95, 0x3e,0x88,
5, Y_INC, TC_ADDR_PORT_95, 0x40,0x0c, // POL TCON7
5, Y_INC, TC_ADDR_PORT_95, 0x41,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x42,0x0D,
5, Y_INC, TC_ADDR_PORT_95, 0x43,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x44,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x45,0x01,
5, Y_INC, TC_ADDR_PORT_95, 0x46,0x8C,
#else
5, Y_INC, TC_ADDR_PORT_95, 0x40,0x0c, // POL TCON7
5, Y_INC, TC_ADDR_PORT_95, 0x41,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x42,0x0D,
5, Y_INC, TC_ADDR_PORT_95, 0x43,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x44,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x45,0x01,
5, Y_INC, TC_ADDR_PORT_95, 0x46,0x88,
// 5, Y_INC, TC_ADDR_PORT_95, 0x46,0x8c,
#endif
//---------------------------------------------------------------
// For RSDS TCON END
//---------------------------------------------------------------
9, Y_INC, LVDS_CTRL0_C0, 0x60,0x04,0x53,0x80,0x80,0x68,
4, N_INC, TC_ADDR_PORT_95, 0x00,
4, N_INC, TC_DATA_PORT_96, 0x80,
0
};
// Be Careful !!
// Display window setting in FreeV[] MUST follow the definition of
// 1. DISP_WID and DISP_LEN
// 2. DH_ACT_STA_POS and DH_ACT_END_POS
// 3. DV_ACT_STA_POS and DV_ACT_END_POS
// 4. Background window must be the same as active window.
unsigned char code FreeV[] =
{
27, Y_INC, VDIS_CTRL_20, 0x20 | DISP_BIT | DISPLAY_PORT, // Disable display timing
0x20 | DISP_INV,
(STD_DH_TOTAL & 0xff), (STD_DH_TOTAL >> 8), // DH_TOTAL
STD_HSYNC_WIDTH, // DH_HS_END
(DH_ACT_STA_POS & 0xff), (DH_ACT_STA_POS >> 8), // DH_BKGD_STA
(DH_ACT_STA_POS & 0xff), (DH_ACT_STA_POS >> 8), // DH_ACT_STA
(DH_ACT_END_POS & 0xff), (DH_ACT_END_POS >> 8), // DH_ACT_END
(DH_ACT_END_POS & 0xff), (DH_ACT_END_POS >> 8), // DH_BKGD_END
(STD_DV_TOTAL & 0xff), (STD_DV_TOTAL >> 8), // DV_TOTAL
STD_VSYNC_LENGTH, // DV_VS_END
(DV_ACT_STA_POS & 0xff), (DV_ACT_STA_POS >> 8) | AUTO_SWITCH, // DV_BKGD_STA
(DV_ACT_STA_POS & 0xff), (DV_ACT_STA_POS >> 8), // DV_ACT_STA
(DV_ACT_END_POS & 0xff), (DV_ACT_END_POS >> 8), // DV_ACT_END
(DV_ACT_END_POS & 0xff), (DV_ACT_END_POS >> 8), // DV_BKGD_END
4, N_INC, VDIS_CTRL_20, 0x23 | DISP_BIT | DISPLAY_PORT, // Enable free-run background
// Force display timing start
6, Y_INC, YUV2RGB_39, 0x00, 0x20 | DCLK_DELAY, 0x04 | DCLK_INV,
4, N_INC, DIS_TIMING0_3A, 0x00 | DCLK_DELAY,
4, N_INC, INT_FLD_DETECT_14, 0x00,
5, Y_INC, IVS_DELAY_8C, 0x00, 0x00,
4, N_INC, SCALE_CTRL_15, 0x00,
4, N_INC, FILTER_CTRL0_1B, 0xc4,
0
};
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