📄 mode_detect.c
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ucSync_Type = SYNC_SS;
RTDCodeW(VGA_SET_SS);
bVpole_Curr = 1;
bHpole_Curr = 1;
}
}
#endif
}
/////////////////////////////////////////////////////////
//------------ Detect VGA & DVI Mode ----------------//
/////////////////////////////////////////////////////////
void Detect_Input_Mode(void)
{
unsigned char ucMode_Temp;
unsigned int usHS_Pulse;
RTDRead(SYNC_POR_4C, 0x09, Y_INC);
if (Data[0] & 0x02)
{
// Reset Sync Processor when sync signal timeout
RTDSetByte(SYNC_POR_4C, ((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA) ? 0x20 : 0x00);
// Treat sync signal timeout as no signal
ucMode_Temp = MODE_NOSIGNAL;
}
else
{
// ucMode_Temp = (Data[8] & 0xe0 ) >> 5;
// if(ucMode_Temp == 0 || ucMode_Temp >=4) //Test which edge of Hsync to latch Vsync will be safe
// {
// RTDSetBit(MEAS_VS_HI_54,0xf7,0x08); //Use positive edge of Hsync to latch Vsync
// ucDebug_Value0 = 0x08;
// }
// else
// {
// RTDSetBit(MEAS_VS_HI_54,0xf7,0x00); //Use negtive edge of Hsync to latch Vsync
// ucDebug_Value0 = 0x18;
// }
usStdHS = usHsync; // Save previous usHsync in usStdHS
usStdVS = usVsync; // Save previous usVsync in usStdVS
bVpole_Curr = (bit)(Data[0] & 0x08); // Save current usVsync polarity
bHpole_Curr = (bit)(Data[0] & 0x04); // Save current usHsync polarity
Data[7] = Data[5];
Data[6] = Data[6] & 0x0f;
Data[5] = Data[3];
Data[4] = Data[4] & 0x87;
Data[3] = Data[1];
Data[2] = Data[2] & 0x8f;
usHsync = ((unsigned int *)Data)[1]; // Current HSYNC timing
usVsync = ((unsigned int *)Data)[2]; // Current VSYNC timing
if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
usHS_Pulse = ((unsigned int *)Data)[3]; // Current HSYNC pulse width
// Calculate Vertical Refresh Rate
// Original Formula :
// ucRefresh = 24.576M / (usHsync * usVsync)
// Use Data[0~3] as a temporary long variable
((unsigned long *)Data)[0] = (unsigned long)usHsync * usVsync;
ucRefresh = (unsigned long)49152000 / ((unsigned long *)Data)[0];
ucRefresh = (ucRefresh & 0x01) ? ((ucRefresh + 1) >> 1) : (ucRefresh >> 1);
// Treat small change of usHsync/usVsync as no change
if (usStdHS <= usHsync && (usStdHS + 2) >= usHsync) usHsync = usStdHS;
if (usStdVS <= usVsync && (usStdVS + 2) >= usVsync) usVsync = usStdVS;
// Polarity must be correct
if ((bVpole_Curr != bVpole_Prev) || (bHpole_Curr != bHpole_Prev))
{
RTDRead(VGIP_SIGINV_05, 0x01, N_INC);
if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
{
Data[0] &= 0xd7; // HS_RAW & VS positive
if (!bHpole_Curr) Data[0] |= 0x20;
if (!bVpole_Curr && SYNC_SS == ucSync_Type) Data[0] |= 0x08; // Seperate sync
ucMode_Temp = MODE_NOSUPPORT;
}
else if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
{
Data[0] &= 0xf3; // VS & HS positive
if (!bVpole_Curr) Data[0] |= 0x08;
if (!bHpole_Curr) Data[0] |= 0x04;
}
RTDSetByte(VGIP_SIGINV_05, Data[0]);
}
else
{
if (0x07ff <= usHsync || 0x07ff <= usVsync || 0 == usHsync || 0 == usVsync)
{
ucMode_Temp = MODE_NOSIGNAL; // Treat overflow as no signal
}
else
{
ucMode_Temp = ((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA) ? VGA_Mode_Search(usHS_Pulse) : MODE_NOSUPPORT;
if (48 > ucRefresh || MAX_RATE < ucRefresh)
{
ucMode_Temp = MODE_NOSUPPORT; // We don't support vertical refresh rate lower than 50Hz
}
else if (MODE_NOSUPPORT == ucMode_Temp && (0 != usIPV_ACT_LEN) && ((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA))
{
ucMode_Temp = Partial_Display();
}
else if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
ucMode_Temp = Seek_DVI_Mode(ucMode_Temp);
// ucDebug_Value0 = ucMode_Temp;
}
}
}
if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
{
if (SYNC_SOG == ucSync_Type && 0 != (usHS_Pulse * 7 / usHsync))
{
// To prevent from SOG mode mistake
// HSYNC pulse width will never longer than 1/7*HSYNC period
ucMode_Temp = MODE_NOSIGNAL;
}
}
//-------------Check result-----------------------------------------
if (MODE_NOSUPPORT == ucMode_Temp || MODE_NOSIGNAL == ucMode_Temp)
{
// Treat illegal signal as no signal when SOG
if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
{
if (SYNC_SOG == ucSync_Type)
ucMode_Temp = MODE_NOSIGNAL;
}
if (MODE_NOSUPPORT != ucMode_Found && MODE_NOSIGNAL != ucMode_Found) ucMode_Times = 0;
ucMode_Found = ucMode_Temp;
if (NO_MODE_TIMES > ucMode_Times)
{
// Wait for signal stable
ucMode_Times ++;
if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
{
//Enable the TMDS Hsync & Vsync error correction to improve the long cable image quality
RTDSetByte(TMDS_CORRECTION_FF,0x03);
}
}
else
{
if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
{
//Disable the TMDS Hsync & Vsync error correction
RTDSetByte(TMDS_CORRECTION_FF,0x00);
}
bStable = (ucMode_Curr == ucMode_Found) ? 1 : 0; // bStable must be cleared when mode changed
ucMode_Curr = ucMode_Found;
ucMode_Times = NO_MODE_TIMES - 2;
if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
Sync_Type_Switch();
}
}
else
{
if (ucMode_Found != ucMode_Temp)
{
ucMode_Times = 1;
ucMode_Found = ucMode_Temp;
if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
Sync_Type_Confirm();
}
else
{
Data[0] = ((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA) ? VGA_SEARCH_TIMES : DVI_SEARCH_TIMES;
//if (VGA_SEARCH_TIMES > ucMode_Times)
if (Data[0] > ucMode_Times)
{
ucMode_Times ++;
}
else
{
bLIGHT_PWR = LIGHT_OFF; // Turn off BackLight for reset display
RTDSetByte(HOSTCTRL_02, 0x40); // Wake RTD up
RTDOSDW(OSD_Reset); // Clear OSD
ucMode_Curr = ucMode_Found; // Supported mode found
ucMode_Times = 0; // Reset mode timer
bStable = 0; // bStable must be cleared when mode changed
if((stGUD1.INPUT_SOURCE & 0x07)== SOURCE_VGA)
Display_VGA_Set(); // Set VGA Mode registers
else
Display_DVI_Set();
#if (RTDDEBUG)
if (ucMode_PrevAct == ucMode_Curr)
{
if (0xff > ucMode_QuitCnt) ucMode_QuitCnt += 1;
}
else
{
ucMode_PrevAct = ucMode_Curr;
ucMode_QuitCnt = 0;
ucDebug = 0;
}
#endif
}
}
}
}
//------------------- Check VGA & DVI Mode -------------------//
void Check_Input_Mode(void)
{
RTDRead(SYNC_POR_4C, 0x05, Y_INC);
if (Data[0] & 0x02)
{
RTDSetByte(SYNC_POR_4C, ((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA) ? 0x20 : 0x00); // Input signal time-out. Reset sync-processor
ucMode_Found = MODE_NOSUPPORT;
}
else
{
bVpole_Curr = (bit)(Data[0] & 0x08); // Current usVsync polarity
bHpole_Curr = (bit)(Data[0] & 0x04); // Current usHsync polarity
Data[5] = Data[3];
Data[4] = Data[4] & 0x87;
Data[3] = Data[1];
Data[2] = Data[2] & 0x8f;
usHsync = ((unsigned int *)Data)[1]; // Current usHsync timing
usVsync = ((unsigned int *)Data)[2]; // Current usVsync timing
// Polarity must be correct
if ((bVpole_Curr != bVpole_Prev) || (bHpole_Curr != bHpole_Prev))
{
RTDRead(VGIP_SIGINV_05, 0x01, N_INC);
/*
Data[0] &= 0xd7; // HS_RAW & VS positive
if (!bHpole_Curr) Data[0] |= 0x20;
if (!bVpole_Curr && SYNC_SS == ucSync_Type) Data[0] |= 0x08; // Seperate sync
*/
if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
{
Data[0] &= 0xd7; // HS_RAW & VS positive
if (!bHpole_Curr) Data[0] |= 0x20;
if (!bVpole_Curr && SYNC_SS == ucSync_Type) Data[0] |= 0x08; // Seperate sync
}
else if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
{
Data[0] &= 0xf3; // VS & HS positive
if (!bVpole_Curr) Data[0] |= 0x08;
if (!bHpole_Curr) Data[0] |= 0x04;
}
RTDSetByte(VGIP_SIGINV_05, Data[0]);
ucMode_Found = MODE_NOSUPPORT;
}
else
{
if (0x07ff <= usHsync || 0x07ff <= usVsync || 0 == usHsync || 0 == usVsync) // Check overflow
{
ucMode_Found = MODE_NOSUPPORT;
}
else
{
if ((usHsync < (usStdHS - 1)) || (usHsync > (usStdHS + 3)) ||
(usVsync < (usStdVS - 1)) || (usVsync > (usStdVS + 3)))
{
ucMode_Found = MODE_NOSUPPORT;
}
else
{
ucMode_Found = ucMode_Curr;
}
}
}
}
if (MODE_NOSUPPORT == ucMode_Found)
Reset_Mode();
else
{
bStable = 1; // Set bStable to 1 when signal timing is stable.
#if(AS_NON_FRAMESYNC)
RTDSetByte(STATUS0_01, 0x00); // Clear status
RTDSetByte(STATUS1_1F, 0x00); // Clear status
if(bFrameSync)
RTDSetBit(ODD_CTRL_8E,0xef,0x10);
#endif
}
}
unsigned char Seek_DVI_Mode(unsigned char mode)
{
#if(TMDS_ENABLE)
unsigned char Wait_Time_Cnt;
RTDSetByte(SYNC_POR_4C, 0x03); // Measure data enable width and height
Wait_Time_Cnt = 60;
do
{
Delay_Xms(1);
RTDRead(SYNC_POR_4C, 0x07, Y_INC);
}
while ((Data[0] & 0x02) && (--Wait_Time_Cnt));
Data[7] = Data[5];
Data[6] = Data[6] & 0x0f;
Data[5] = Data[3];
Data[4] = Data[4] & 0x87;
Data[3] = Data[1];
Data[2] = Data[2] & 0x8f;
// Measure Failed !!!
if ((0 == ((unsigned int *)Data)[1]) || (0x07ff <= ((unsigned int *)Data)[1]) ||
(0 == ((unsigned int *)Data)[2]) || (0x07ff <= ((unsigned int *)Data)[2]) ||
(0 == Wait_Time_Cnt))
{
RTDSetByte(SYNC_POR_4C, 0x00);
return MODE_NOSUPPORT;
}
// Save IH_TOTAL in usADC_Clock
usADC_Clock = ((unsigned int *)Data)[1] * 2;
// Save input data enable width and height
usIPV_ACT_LEN = ((unsigned int *)Data)[2];
usIPH_ACT_WID = ((unsigned int *)Data)[3] * 2;
// We don't support input image less than 350 active lines
if (350 > usIPV_ACT_LEN) return MODE_NOSUPPORT;
// We only support 8N active width
usIPH_ACT_WID = (2 < (usIPH_ACT_WID & 0x0007)) ? ((usIPH_ACT_WID + 8) & 0xfff8) : (usIPH_ACT_WID & 0xfff8);
// We only support active width not larger than 1280
if (1280 < usIPH_ACT_WID) usIPH_ACT_WID = 1280;
// Calculate maximum usIPV_ACT_LEN limitation
((unsigned int *)Data)[0] = (unsigned long)(usVsync - 1) * DISP_LEN / MIN_DV_TOTAL;
if (((unsigned int *)Data)[0] < usIPV_ACT_LEN) usIPV_ACT_LEN = ((unsigned int *)Data)[0];
mode = MODE_UNDEFINED0;
if (MODE_UNDEFINED0 == mode)
{
// First, we try user-mode to fit the undefined mode for full-screen display.
Wait_Time_Cnt = MODE_USER720x400;
do
{
if (Mode_Preset[Wait_Time_Cnt][2] < CAP_WIN[Wait_Time_Cnt][4]) // V scale-down
{
// Larger scale-down ratio may need a larger DH_TOTAL.
// So usIPV_ACT_LEN should not be too larger than pre-set capture window length
if (Mode_Preset[Wait_Time_Cnt][2] > usIPV_ACT_LEN || (CAP_WIN[Wait_Time_Cnt][4] + 24) < usIPV_ACT_LEN) continue;
}
else
{
if (Mode_Preset[Wait_Time_Cnt][2] < usIPV_ACT_LEN) continue;
}
((unsigned int *)Data)[0] = (unsigned long)2458 * Mode_Preset[Wait_Time_Cnt][0] * Mode_Preset[Wait_Time_Cnt][2]
/ ((unsigned long)100 * usIPV_ACT_LEN * usHsync);
// Return if we find out a suitable user-mode.
if (MAX_DCLK > ((unsigned int *)Data)[0]) return Wait_Time_Cnt;
}
while (MODE_USER1600x1200 >= ++Wait_Time_Cnt);
mode = Partial_Display();
// If failed, we try partial-screen display.
}
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