📄 mode_detect.lst
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492 2
493 2 // Polarity must be correct
494 2 if ((bVpole_Curr != bVpole_Prev) || (bHpole_Curr != bHpole_Prev))
495 2 {
496 3 RTDRead(VGIP_SIGINV_05, 0x01, N_INC);
497 3
498 3 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
499 3 {
500 4 Data[0] &= 0xd7; // HS_RAW & VS positive
501 4
502 4 if (!bHpole_Curr) Data[0] |= 0x20;
503 4
504 4 if (!bVpole_Curr && SYNC_SS == ucSync_Type) Data[0] |= 0x08; // Seperate sync
505 4
506 4 ucMode_Temp = MODE_NOSUPPORT;
507 4 }
508 3 else if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
509 3 {
510 4 Data[0] &= 0xf3; // VS & HS positive
511 4
512 4 if (!bVpole_Curr) Data[0] |= 0x08;
513 4 if (!bHpole_Curr) Data[0] |= 0x04;
514 4 }
515 3 RTDSetByte(VGIP_SIGINV_05, Data[0]);
516 3
517 3
518 3 }
519 2 else
520 2 {
521 3 if (0x07ff <= usHsync || 0x07ff <= usVsync || 0 == usHsync || 0 == usVsync)
522 3 {
523 4 ucMode_Temp = MODE_NOSIGNAL; // Treat overflow as no signal
524 4 }
525 3 else
526 3 {
527 4 ucMode_Temp = ((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA) ? VGA_Mode_Search(usHS_Pulse) :
- MODE_NOSUPPORT;
528 4
529 4
530 4 if (48 > ucRefresh || MAX_RATE < ucRefresh)
531 4 {
532 5 ucMode_Temp = MODE_NOSUPPORT; // We don't support vertical refresh rate lower than 5
-0Hz
533 5 }
534 4 else if (MODE_NOSUPPORT == ucMode_Temp && (0 != usIPV_ACT_LEN) && ((stGUD1.INPUT_SOURCE &
-0x07) == SOURCE_VGA))
535 4 {
536 5 ucMode_Temp = Partial_Display();
537 5 }
538 4 else if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
539 4 ucMode_Temp = Seek_DVI_Mode(ucMode_Temp);
540 4
541 4 // ucDebug_Value0 = ucMode_Temp;
542 4 }
543 3 }
544 2 }
545 1
546 1 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 10
547 1 {
548 2 if (SYNC_SOG == ucSync_Type && 0 != (usHS_Pulse * 7 / usHsync))
549 2 {
550 3 // To prevent from SOG mode mistake
551 3 // HSYNC pulse width will never longer than 1/7*HSYNC period
552 3 ucMode_Temp = MODE_NOSIGNAL;
553 3 }
554 2 }
555 1
556 1 //-------------Check result-----------------------------------------
557 1 if (MODE_NOSUPPORT == ucMode_Temp || MODE_NOSIGNAL == ucMode_Temp)
558 1 {
559 2 // Treat illegal signal as no signal when SOG
560 2 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
561 2 {
562 3 if (SYNC_SOG == ucSync_Type)
563 3 ucMode_Temp = MODE_NOSIGNAL;
564 3 }
565 2
566 2 if (MODE_NOSUPPORT != ucMode_Found && MODE_NOSIGNAL != ucMode_Found) ucMode_Times = 0;
567 2
568 2 ucMode_Found = ucMode_Temp;
569 2
570 2 if (NO_MODE_TIMES > ucMode_Times)
571 2 {
572 3 // Wait for signal stable
573 3 ucMode_Times ++;
574 3
575 3 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
576 3 {
577 4 //Enable the TMDS Hsync & Vsync error correction to improve the long cable image quality
578 4 RTDSetByte(TMDS_CORRECTION_FF,0x03);
579 4 }
580 3 }
581 2 else
582 2 {
583 3 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
584 3 {
585 4 //Disable the TMDS Hsync & Vsync error correction
586 4 RTDSetByte(TMDS_CORRECTION_FF,0x00);
587 4 }
588 3
589 3 bStable = (ucMode_Curr == ucMode_Found) ? 1 : 0; // bStable must be cleared when mo
-de changed
590 3 ucMode_Curr = ucMode_Found;
591 3 ucMode_Times = NO_MODE_TIMES - 2;
592 3
593 3 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
594 3 Sync_Type_Switch();
595 3
596 3 }
597 2 }
598 1 else
599 1 {
600 2 if (ucMode_Found != ucMode_Temp)
601 2 {
602 3 ucMode_Times = 1;
603 3 ucMode_Found = ucMode_Temp;
604 3
605 3 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
606 3 Sync_Type_Confirm();
607 3 }
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 11
608 2 else
609 2 {
610 3 Data[0] = ((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA) ? VGA_SEARCH_TIMES : DVI_SEARCH_TIMES;
611 3 //if (VGA_SEARCH_TIMES > ucMode_Times)
612 3 if (Data[0] > ucMode_Times)
613 3 {
614 4 ucMode_Times ++;
615 4 }
616 3 else
617 3 {
618 4
619 4 bLIGHT_PWR = LIGHT_OFF; // Turn off BackLight for reset display
620 4
621 4 RTDSetByte(HOSTCTRL_02, 0x40); // Wake RTD up
622 4 RTDOSDW(OSD_Reset); // Clear OSD
623 4
624 4 ucMode_Curr = ucMode_Found; // Supported mode found
625 4 ucMode_Times = 0; // Reset mode timer
626 4 bStable = 0; // bStable must be cleared when mode changed
627 4
628 4 if((stGUD1.INPUT_SOURCE & 0x07)== SOURCE_VGA)
629 4 Display_VGA_Set(); // Set VGA Mode registers
630 4 else
631 4 Display_DVI_Set();
632 4
633 4
634 4 #if (RTDDEBUG)
if (ucMode_PrevAct == ucMode_Curr)
{
if (0xff > ucMode_QuitCnt) ucMode_QuitCnt += 1;
}
else
{
ucMode_PrevAct = ucMode_Curr;
ucMode_QuitCnt = 0;
ucDebug = 0;
}
#endif
646 4 }
647 3 }
648 2 }
649 1 }
650
651 //------------------- Check VGA & DVI Mode -------------------//
652 void Check_Input_Mode(void)
653 {
654 1 RTDRead(SYNC_POR_4C, 0x05, Y_INC);
655 1
656 1 if (Data[0] & 0x02)
657 1 {
658 2 RTDSetByte(SYNC_POR_4C, ((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA) ? 0x20 : 0x00); // I
-nput signal time-out. Reset sync-processor
659 2
660 2 ucMode_Found = MODE_NOSUPPORT;
661 2 }
662 1 else
663 1 {
664 2 bVpole_Curr = (bit)(Data[0] & 0x08); // Current usVsync polarity
665 2 bHpole_Curr = (bit)(Data[0] & 0x04); // Current usHsync polarity
666 2
667 2 Data[5] = Data[3];
668 2 Data[4] = Data[4] & 0x87;
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 12
669 2 Data[3] = Data[1];
670 2 Data[2] = Data[2] & 0x8f;
671 2 usHsync = ((unsigned int *)Data)[1]; // Current usHsync timing
672 2 usVsync = ((unsigned int *)Data)[2]; // Current usVsync timing
673 2
674 2 // Polarity must be correct
675 2 if ((bVpole_Curr != bVpole_Prev) || (bHpole_Curr != bHpole_Prev))
676 2 {
677 3 RTDRead(VGIP_SIGINV_05, 0x01, N_INC);
678 3 /*
679 3 Data[0] &= 0xd7; // HS_RAW & VS positive
680 3
681 3 if (!bHpole_Curr) Data[0] |= 0x20;
682 3
683 3 if (!bVpole_Curr && SYNC_SS == ucSync_Type) Data[0] |= 0x08; // Seperate sync
684 3 */
685 3
686 3
687 3 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
688 3 {
689 4 Data[0] &= 0xd7; // HS_RAW & VS positive
690 4
691 4 if (!bHpole_Curr) Data[0] |= 0x20;
692 4
693 4 if (!bVpole_Curr && SYNC_SS == ucSync_Type) Data[0] |= 0x08; // Seperate sync
694 4 }
695 3 else if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
696 3 {
697 4 Data[0] &= 0xf3; // VS & HS positive
698 4
699 4 if (!bVpole_Curr) Data[0] |= 0x08;
700 4 if (!bHpole_Curr) Data[0] |= 0x04;
701 4 }
702 3
703 3 RTDSetByte(VGIP_SIGINV_05, Data[0]);
704 3
705 3 ucMode_Found = MODE_NOSUPPORT;
706 3 }
707 2 else
708 2 {
709 3 if (0x07ff <= usHsync || 0x07ff <= usVsync || 0 == usHsync || 0 == usVsync) // Check overf
-low
710 3 {
711 4 ucMode_Found = MODE_NOSUPPORT;
712 4 }
713 3 else
714 3 {
715 4 if ((usHsync < (usStdHS - 1)) || (usHsync > (usStdHS + 3)) ||
716 4 (usVsync < (usStdVS - 1)) || (usVsync > (usStdVS + 3)))
717 4 {
718 5 ucMode_Found = MODE_NOSUPPORT;
719 5 }
720 4 else
721 4 {
722 5 ucMode_Found = ucMode_Curr;
723 5 }
724 4 }
725 3 }
726 2 }
727 1
728 1 if (MODE_NOSUPPORT == ucMode_Found)
729 1 Reset_Mode();
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 13
730 1 else
731 1 {
732 2 bStable = 1; // Set bStable to 1 when signal timing is stable.
733 2 #if(AS_NON_FRAMESYNC)
RTDSetByte(STATUS0_01, 0x00); // Clear status
RTDSetByte(STATUS1_1F, 0x00); // Clear status
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