📄 mode_detect.lst
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242 3 // If clock rate for full-screen display is too high, we can try partial-V display.
243 3 // Estimate clock for partial-V display
244 3 // DCLK = (24.576MHz / usHsync) * DCLK per display line * (min. display total lines / input total lines
-)
245 3 ((unsigned int *)Data)[1] = (unsigned long)2458 * Mode_Preset[MODE_UNDEFINED1][0] * MIN_DV_TOTAL
246 3 / ((unsigned long)100 * (usVsync - 1) * usHsync);
247 3
248 3 if (MAX_DCLK < ((unsigned int *)Data)[1])
249 3 {
250 4 // Decrease usIPV_ACT_LEN to DISP_LEN and go further to check if it can be displayed.
251 4 usIPV_ACT_LEN = DISP_LEN;
252 4 }
253 3 else
254 3 {
255 4 ucMode_Temp = MODE_UNDEFINED1 | 0x80; // Scale-down and partial-V display
256 4 }
257 3 }
258 2 else
259 2 ucMode_Temp = MODE_UNDEFINED1; // Scale-down and full-V display
260 2 }
261 1
262 1 if (DISP_LEN >= usIPV_ACT_LEN) // V Scale-up
263 1 {
264 2 ((unsigned int *)Data)[0] = (unsigned long)2458 * Mode_Preset[MODE_UNDEFINED0][0] * DISP_LEN
265 2 / ((unsigned long)100 * usIPV_ACT_LEN * usHsync);
266 2
267 2 if (MAX_DCLK < ((unsigned int *)Data)[0])
268 2 {
269 3 if (MIN_DV_TOTAL >= (usVsync - 1))
270 3 {
271 4 ((unsigned int *)Data)[1] = (unsigned long)2458 * Mode_Preset[MODE_UNDEFINED0][0] * MIN_DV_TOTAL
272 4 / ((unsigned long)100 * (usVsync - 1) * usHsync);
273 4 }
274 3 else
275 3 {
276 4 ((unsigned int *)Data)[1] = (unsigned long)2458 * Mode_Preset[MODE_UNDEFINED0][0]
277 4 / ((unsigned long)100 * usHsync);
278 4 }
279 3
280 3 if (MAX_DCLK < ((unsigned int *)Data)[1])
281 3 ucMode_Temp = MODE_NOSUPPORT; // Cannot display
282 3 else
283 3 ucMode_Temp = MODE_UNDEFINED0 | 0x80; // Scale-up and partial-V display
284 3 }
285 2 else
286 2 ucMode_Temp = MODE_UNDEFINED0; // Scale-up and full-V display
287 2 }
288 1
289 1 return ucMode_Temp;
290 1
291 1 }
292
293 void Sync_Type_Switch(void)
294 {
295 1 if (MODE_NOSIGNAL == ucMode_Curr)
296 1 {
297 2 if (SYNC_CS == ucSync_Type) // CS->SS
298 2 {
299 3 RTDCodeW(VGA_SET_SS);
300 3
301 3 bVpole_Curr = 1;
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 6
302 3 bHpole_Curr = 1;
303 3 ucSync_Type = SYNC_SS;
304 3
305 3 }
306 2 else if (SYNC_SS == ucSync_Type) // SS->SOG
307 2 {
308 3 RTDCodeW(VGA_SET_SOG);
309 3
310 3 bVpole_Curr = 1;
311 3 bHpole_Curr = 1;
312 3 ucSync_Type = SYNC_SOG;
313 3
314 3
315 3
316 3 }
317 2 else // SOG->CS
318 2 {
319 3 RTDCodeW(VGA_SET_CS);
320 3
321 3 bVpole_Curr = 1;
322 3 bHpole_Curr = 1;
323 3 ucSync_Type = SYNC_CS;
324 3
325 3
326 3
327 3 }
328 2 }
329 1 }
330
331 void Sync_Type_Confirm(void)
332 {
333 1
334 1 #if(SOURCE_AUTO_SCAN == _FALSE)
unsigned char m;
// To prevent from mistaking CS (with VS) for SS, we check SYNC type once when finding a mode in SS.
if (SYNC_SS == ucSync_Type)
{
RTDSetByte(SYNC_CTRL_4B, 0x55);
RTDSetByte(SYNC_POR_4C, 0x22);
m = (MODE_DETECT_FREQ + 1) * 20;
do
{
Delay_Xms(1);
RTDRead(SYNC_POR_4C, 0x05, Y_INC);
}
while ((Data[0] & 0x02) && (--m));
Data[5] = Data[3];
Data[4] = Data[4] & 0x87;
Data[3] = Data[1];
Data[2] = Data[2] & 0x8f;
if ((0 == ((unsigned int *)Data)[1]) || (0x07ff <= ((unsigned int *)Data)[1]) ||
(0 == ((unsigned int *)Data)[2]) || (0x07ff <= ((unsigned int *)Data)[2]) ||
(0 == m))
{
ucSync_Type = SYNC_SS;
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 7
RTDSetByte(SYNC_CTRL_4B, 0x14);
}
else
{
ucSync_Type = SYNC_CS;
RTDCodeW(VGA_SET_CS);
bVpole_Curr = 1;
bHpole_Curr = 1;
}
}
else if (SYNC_SOG == ucSync_Type)
{
RTDSetByte(SYNC_CTRL_4B, 0x14);
Delay_Xms(8);
RTDSetByte(SYNC_POR_4C, 0x00);
RTDSetByte(SYNC_POR_4C, 0x02);
m = (MODE_DETECT_FREQ + 1) * 20;
do
{
Delay_Xms(1);
RTDRead(SYNC_POR_4C, 0x05, Y_INC);
}
while ((Data[0] & 0x02) && (--m));
Data[5] = Data[3];
Data[4] = Data[4] & 0x87;
Data[3] = Data[1];
Data[2] = Data[2] & 0x8f;
if ((0 == ((unsigned int *)Data)[1]) || (0x07ff <= ((unsigned int *)Data)[1]) ||
(0 == ((unsigned int *)Data)[2]) || (0x07ff <= ((unsigned int *)Data)[2]) ||
(0 == m))
{
ucSync_Type = SYNC_SOG;
RTDSetByte(SYNC_CTRL_4B, 0x57);
//RTDSetByte(VGIP_SIGINV_05, 0x40);
Delay_Xms(8);
RTDSetByte(SYNC_POR_4C,0x32);
Delay_Xms(20);
RTDSetByte(SYNC_POR_4C, 0x00);
}
else
{
ucSync_Type = SYNC_SS;
RTDCodeW(VGA_SET_SS);
bVpole_Curr = 1;
bHpole_Curr = 1;
}
}
#endif
425 1
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 8
426 1 }
427 /////////////////////////////////////////////////////////
428 //------------ Detect VGA & DVI Mode ----------------//
429 /////////////////////////////////////////////////////////
430 void Detect_Input_Mode(void)
431 {
432 1 unsigned char ucMode_Temp;
433 1 unsigned int usHS_Pulse;
434 1
435 1 RTDRead(SYNC_POR_4C, 0x09, Y_INC);
436 1
437 1 if (Data[0] & 0x02)
438 1 {
439 2 // Reset Sync Processor when sync signal timeout
440 2 RTDSetByte(SYNC_POR_4C, ((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA) ? 0x20 : 0x00);
441 2
442 2 // Treat sync signal timeout as no signal
443 2 ucMode_Temp = MODE_NOSIGNAL;
444 2 }
445 1 else
446 1 {
447 2
448 2 // ucMode_Temp = (Data[8] & 0xe0 ) >> 5;
449 2
450 2 // if(ucMode_Temp == 0 || ucMode_Temp >=4) //Test which edge of Hsync to latch Vsync will be safe
451 2 // {
452 2 // RTDSetBit(MEAS_VS_HI_54,0xf7,0x08); //Use positive edge of Hsync to latch Vsync
453 2 // ucDebug_Value0 = 0x08;
454 2 // }
455 2 // else
456 2 // {
457 2 // RTDSetBit(MEAS_VS_HI_54,0xf7,0x00); //Use negtive edge of Hsync to latch Vsync
458 2 // ucDebug_Value0 = 0x18;
459 2 // }
460 2
461 2
462 2 usStdHS = usHsync; // Save previous usHsync in usStdHS
463 2 usStdVS = usVsync; // Save previous usVsync in usStdVS
464 2
465 2 bVpole_Curr = (bit)(Data[0] & 0x08); // Save current usVsync polarity
466 2 bHpole_Curr = (bit)(Data[0] & 0x04); // Save current usHsync polarity
467 2
468 2 Data[7] = Data[5];
469 2 Data[6] = Data[6] & 0x0f;
470 2 Data[5] = Data[3];
471 2 Data[4] = Data[4] & 0x87;
472 2 Data[3] = Data[1];
473 2 Data[2] = Data[2] & 0x8f;
474 2
475 2 usHsync = ((unsigned int *)Data)[1]; // Current HSYNC timing
476 2 usVsync = ((unsigned int *)Data)[2]; // Current VSYNC timing
477 2
478 2 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
479 2 usHS_Pulse = ((unsigned int *)Data)[3]; // Current HSYNC pulse width
480 2
481 2 // Calculate Vertical Refresh Rate
482 2 // Original Formula :
483 2 // ucRefresh = 24.576M / (usHsync * usVsync)
484 2 // Use Data[0~3] as a temporary long variable
485 2 ((unsigned long *)Data)[0] = (unsigned long)usHsync * usVsync;
486 2 ucRefresh = (unsigned long)49152000 / ((unsigned long *)Data)[0];
487 2 ucRefresh = (ucRefresh & 0x01) ? ((ucRefresh + 1) >> 1) : (ucRefresh >> 1);
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 9
488 2
489 2 // Treat small change of usHsync/usVsync as no change
490 2 if (usStdHS <= usHsync && (usStdHS + 2) >= usHsync) usHsync = usStdHS;
491 2 if (usStdVS <= usVsync && (usStdVS + 2) >= usVsync) usVsync = usStdVS;
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