📄 fwxsc1.s.bak
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ldr r1, =FFUART_BASE_PHYSICAL ; Tx start
PrintStr r1, r2, r3
bl Main ;// change add
ldr r0, =0xA0000000 ; phy start Adx
IF SABINAL != "1"
mov r1, #64 ; #MB bman: must make this conditional based on #mb populated
ELSE
mov r1, #32
ENDIF
SCRUB_SDRAM r0, r1, r2, r3
add r2, pc, #END_SCRUBBING-(.+8)
ldr r1, =FFUART_BASE_PHYSICAL ; Tx end
PrintStr r1, r2, r3
ENDIF ; _FLASH.
b END_DISPLAY
Got_SLEEP_RESET
ldr r1, =FFUART_BASE_PHYSICAL ; Tx end
add r2, pc, #SLEEP_RST_STR-(.+8) ;
PrintStr r1, r2, r3
b END_DISPLAY
Got_GPIO_RESET
ldr r1, =FFUART_BASE_PHYSICAL ; Tx end
ldr r2, =(SOFT_RST_STR-(.+8)) ; Tx end
add r2, pc, r2 ;
PrintStr r1, r2, r3
b END_DISPLAY
END_DISPLAY
mov pc, lr
LTORG ; Insert a literal pool here
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;; Data used for FFUART Transmissions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; SDCLK[1] Banners
;
ALIGN
SDCLK_HALF_MSG DCB " SDCLK[1] = MemClk/2", 0xA, 0xD, 0
ALIGN
SDCLK_EQU_MSG DCB " SDCLK[1] = MemClk", 0xA, 0xD, 0
;
; CCCR[L] Banners
;
ALIGN
L_09 DCB " MemClk = 33.2 MHz", 0xA, 0xD, 0
ALIGN
L_27 DCB " MemClk = 99.53 MHz", 0xA, 0xD, 0
ALIGN
L_32 DCB " MemClk = 117.96 MHz", 0xA, 0xD, 0
ALIGN
L_36 DCB " MemClk = 132.71 MHz", 0xA, 0xD, 0
ALIGN
L_40 DCB " MemClk = 147.46 MHz", 0xA, 0xD, 0
ALIGN
L_45 DCB " MemClk = 165.89 MHz", 0xA, 0xD, 0
;
; CCCR[M} Banners
;
ALIGN
M_1 DCB " Run Mode = MemClk", 0xA, 0xD, 0
ALIGN
M_2 DCB " Run Mode = 2 * MemClk", 0xA, 0xD, 0
ALIGN
M_3 DCB " Run Mode = 4 * MemClk", 0xA, 0xD, 0
;
; CCCR[N] Banners
;
ALIGN
N_1 DCB " Turbo Mode = Run Mode", 0xA, 0xD, 0
ALIGN
N_15 DCB " Turbo Mode = 1.5 * Run Mode", 0xA, 0xD, 0
ALIGN
N_2 DCB " Turbo Mode = 2 * Run Mode", 0xA, 0xD, 0
ALIGN
N_25 DCB " Turbo Mode = 2.5 * Run Mode", 0xA, 0xD, 0
ALIGN
N_3 DCB " Turbo Mode = 3 * Run Mode", 0xA, 0xD, 0
;
; Run/Turbo Mode Banners
;
ALIGN
RUNMODE DCB "Mode: RUN", 0xA, 0xD, 0xA, 0xD, 0
ALIGN
TURBOMODE DCB "Mode: TURBO", 0xA, 0xD, 0xA, 0xD, 0
;
; Misc. Strings
;
ALIGN
START_SCRUBBING DCB 0xA, 0xD, "2005-09-18Beginning SDRAM Scrub...", 0xA, 0xD, 0
ALIGN
END_SCRUBBING DCB "XXXX9999999SDRAM Scrub Complete", 0xA, 0xD, 0
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
INITMMU
; *****************************************************************
; Load RVA of OEMAddressTable[]
;
add r0, pc, #OEMAddressTable-(.+8) ; (r0) = OEMAddressTable phys addr
mov r11, r0 ; (r11) = &MemoryMap (save pointer)
IF :LNOT: :DEF: ETHBOOT
bl KernelStart ; Branch to coreos\armtrap.s::KernelStart()
; should not return, NK now in control
nop
nop
nop
DEADLOOP
b DEADLOOP
ENDIF ; :LNOT: :DEF: ETHBOOT
; For GPIO / soft reset, don't go to Eboot main(), go to launch address from load.
tst r10, #RCSR_GPIO_RESET
beq CONTINUE
ldr r4, =(SLEEPDATA_BASE_PHYSICAL+Reset_LaunchAddr) ; get pointer to SLEEPDATA
ldr r3, [r4] ; Get previously saved launch address
ldr r2, =PhysicalStart
;
; First, we need to find the Offset that will get us from Virtual->Phyiscal for
; the EBOOT Partition
;
ldr r5, =(EBOOT_PARTITION_PHY_BASE - SDRAM_VIR_C_EBOOT_PARTITION)
;
; Next, we add the above found Offset to PhysicalStart's RVA.
; (R2 now points to the Physical address of PhysicalStart (below).)
;
add r2, r2, r5
IF Interworking :LOR: Thumbing
bx r2
ELSE
mov pc, r2
ENDIF
nop ; These NOPs are used to flush the Pipeline
nop
nop
nop
b CONTINUE ; branch around Include (do not move)
INCLUDE MemMap.inc ; **NOTE: DO NOT move this! Must be in this section
CONTINUE
; *****************************************************************
; Copy Flash-based Eboot image into RAM. This will be placed
; in our EBOOT_PARTITION plus an offset. (EbootOffset)
;
;
; The bootloader is linked to run from RAM but is initially installed in "FLASH" Ram
; at the reset/boot address. Now that memory has been configured, copy the
; entire bootloader image to RAM.
;
; *Note: The bootloader's region size must agree with boot.bib's declaration of
; it.
;
ldr r8, =BOOT_FLASH_BASE_PHYSICAL ; Phy Base of our EBOOT PARTITION
ldr r1, =(EBOOT_PARTITION_PHY_BASE + EbootOffset) ; **Defined in BOOT.BIB. Is the offset into the EBOOT PARTITION.
; This (and next) values must match BOOT.BIB!
ldr r2, =(EBootImageLen/16) ; Setup Loop control. We are block-copying 16-bytes per iteration.
; **EBootImageLen From BOOT.BIB, size field.
;
; Do 4x32-bit Block Copies from Flash->SDRAM (corrupts r4-r7)
;
10 ldmia r8!, {r4-r7} ; Loads from BOOT_FLASH_BASE_PHYSICAL, post increment
stmia r1!, {r4-r7} ; Stores to (EBOOT_PARTITION_PHY_BASE+EbootOffset), post increment
subs r2, r2, #1
bne %B10
;
; Now that we have copied ourselves into RAM, jump to RAM's 'CodeInRAM' Label and start there
;
add r2, pc, #CodeInRAM-(.+8) ; Calc. PC-relative address of 'CodeInRAM'
ldr r1, =(EBOOT_PARTITION_PHY_BASE + EbootOffset) ; Load Phy Adx of where we started our copy above
add r1, r1, r2 ; Calc. Phy Adx of 'CodeInRAM' tag
IF Interworking :LOR: Thumbing
bx r1
ELSE
mov pc, r1
ENDIF
nop
nop
nop
CodeInRAM
BUILDTTB
; *****************************************************************
; *****************************************************************
; *****************************************************************
; *****************************************************************
; *****************************************************************
; Fill in first-level Section descriptors to create 1MB mapped regions
; from the contents of the MemoryMap array. (OEMAddressTable[])
;
; (r9) = TTB
; (r11) = ptr to MemoryMap array
;
;
; We split the mappings: [8000 0000 --> 9FFF FFFF] = Cacheable, Bufferable
; [A000 0000 --> BFFF FFFF] = NonCacheable, nonBufferable
;
;;;;; **************************************
; All code below is EBOOT-specific
; (i.e. NOT used by winCE)
; **************************************
;
; First, make copy of r9 (CPUId)
;
mov r7, r9
ldr r3, =B2_STEPPING ; Load the B2 Stepping value
and r7, r7, #0xF ; Grab only the lowest nibble as it's all we care about
;
; Set TTB
;
ldr r9, =EBOOT_PARTITION_PHY_BASE ; (r9) = physical address of 1st level table (EBOOT partition base) 0xA000 0000
ldr r0, =0xFFFFC000
and r9, r9, r0 ; mask off TTB[31:0] (must be 0's)
mcr p15, 0, r9, c2, c0, 0 ; set TTB
; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; ~~~~~~~~~~ MAP CACHEABLE. BUFFERABLE SECTION DESCRIPTORS ~~~~~~~~~~~~~~~~
; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;
; Workaround for De Soto Core Errata Part I: Configure cacheable sections as Write-Through for cores <=B1.
; *NOTE: Once we know what Sabinal.B1's CPUID looks like, we need to ensure this workaround happens for De Soto Sabinals.
;
cmp r7, r3 ; what stepping of CPU? If <=B2, need to ensure _all_ descriptors are marked Write-Through, Read-Allocate (C=1, B=0).
movle r0, #0x0A ; (r0) = Section (1MB) Descriptor; C=1, B=0. Write-Through, Read-Allocate
movgt r0, #0x0E ; (r0) = Section (1MB) Descriptor; C=B=1. Write-Back, Read-Allocate
orr r0, r0, #0x400 ; set AP
20 mov r1, r11 ; (r1) = ptr to MemoryMap array
;
; Start Crunching through the OEMAddressTable[]
;
; r2 temporarily holds OEMAddressTable[VA]
; r3 temporarily holds OEMAddressTable[PHY]
; r4 temporarily holds OEMAddressTable[#MB]
;
25
ldr r2, [r1], #4 ; (r2) = virtual, Cached address to map Bank at
ldr r3, [r1], #4 ; (r3) = physical address to map from
ldr r4, [r1], #4 ; (r4) = num MB to map
cmp r4, #0 ; End of table?
beq %F29
;****************************************************************************************************************************************************************
; (r2) holds the &descriptor
; (r0) holds the actual section descriptor
;
; Create Descriptor Address
;
ldr r6, =0xFFF00000
and r2, r2, r6 ; only VA[31:20] are valid
orr r2, r9, r2, LSR #18 ; build the descriptor address: r2 = (TTB[31:14} | VA[31:20] >> 18)
; Create the Descriptor
;
ldr r6, =0xFFF00000
and r3, r3, r6 ; only PA[31:20] are valid for the descriptor; rest will be static
orr r0, r3, r0 ; build the descriptor: r0 = (PA[31:20] | the rest of the descriptor)
; Store the descriptor at the proper (phy) address
;
28 str r0, [r2], #4
add r0, r0, #0x00100000 ; (r0) = THE Section descriptor for the next 1MB mapping (just add 1MB)
sub r4, r4, #1 ; Decrement number of MB left
cmp r4, #0
bne %B28 ; Map next MB
bic r0, r0, #0xF0000000 ; Clear Section Base Address Field
bic r0, r0, #0x0FF00000 ; Clear Section Base Address Field
b %B25 ; Get and process next table element
; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;
; Next, go through the above loop construct again.
; This time, we will map C=B=0 space (i.e. uncached, nonbuffered)
;
29
tst r0, #8 ; Test for 'C' bit set (means we just used above loop structure to map Cacheable,Bufferable space)
bic r0, r0, #0x0C ; clear cachable & bufferable bits in Descriptor (clear C&B bits)
add r9, r9, #0x0800 ; (r9) = ptr to 1st PTE for "unmapped uncached space" (0x2000 0000 + V_U_Adx)
bne %B20 ; go setup Descriptors for uncached space (map C=B=0 space)
ACTIVATEMMU
; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
; The 1st Level Section Descriptors are setup. Initialize the MMU and turn it on.
;
bl Main ;// change add
mov r1, #1
mcr p15, 0, r1, c3, c0, 0 ; setup access to domain 0
mcr p15, 0, r0, c8, c7, 0 ; flush I+D TLBs
mcr p15, 0, r1, c7, c10, 4 ; drain write and fill buffers
mov r1, #0x78 ; bits [6:3] must be written as 1's
orr r1, r1, #0x1 ; Enable: MMU
orr r1, r1, #0x1000 ; Enable icache
orr r1, r1, #0x0800 ; Enable BTB
orr r1, r1, #0x4 ; Enable Data Cache
ldr r2, =VirtualStart ; RVA
cmp r2, #0 ; make sure no stall on "mov pc,r2" below
;
; *Flip the MMU ON*
;
mcr p15, 0, r1, c1, c0, 0 ; MMU ON: All mem accesses now ~Virtual~
ldr r3, =B2_STEPPING ; Load the B2 Stepping value
cmp r7, r3 ; r7 still contains the cpuid
bgt GOVIRTUAL ; workaround not needed for >B2
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