📄 fwxsc1.s.bak
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ldr r3, [r1, #MDREFR_OFFSET]
; enable auto-power down
;
orr r3, r3, #MDREFR_APD
; write back mdrefr
;
str r3, [r1, #MDREFR_OFFSET]
ENDIF ; // IF 0
;... ENDIF ; // A1_Cotulla & A1_Sabinal
mov pc, lr
LTORG ; Insert a literal pool here
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
INITOST
; ********************************************************************
; Initialize the OST count register to zero.
;
ldr r1, =OSCR_BASE_PHYSICAL
mov r2, #0
str r2, [r1]
mov pc, lr
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
INITRTC
; ********************************************************************
; Initialize the RTC count register to zero. Currently not adjusting
; the trim reg (RTTR).
;
ldr r1, =RCNR_BASE_PHYSICAL
mov r2, #0
str r2, [r1]
mov pc, lr
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
INITPWRMAN
; ********************************************************************
; Initialize the power mgr registers.
;
; get base address of power mgr / reset control regs
;
ldr r2, =PWR_BASE_PHYSICAL
;
; set the immediate sleep mode on batt/vdd fault
;
;;;;;; Move to immediately after reset, because cleared by resets!
; mov r1, #1 ; force Imprecise Data Abort on Fault
; str r1, [r2, #PMCR_OFFSET]
; initialize the pcfr
;
mov r1, #PCFR_OPDE ; enable 3.68Mhz power-down during sleep
orr r1, r1, #PCFR_FP ; enable PCMCIA pin float during sleep
orr r1, r1, #PCFR_FS ; enable static memory pin float during sleep
bic r1, r1, #PCFR_DS ; disable deep-sleep mode
str r1, [r2, #PCFR_OFFSET]
; initialize the pwer
;
mov r1, #PWER_WE0 ; enable gpio0 wakeup
orr r1, r1, #PWER_WE1 ; enable gpio1 wakeup
orr r1, r1, #PWER_WERTC ; enable rtc alarm wakeup
str r1, [r2, #PWER_OFFSET]
mov pc, lr
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
ENABLECLKS
; Re-Enable On-Chip Peripheral Clocking
; *Note: Currently enabling: ALL 17 clocks.
ldr r1, =CKEN_BASE_PHYSICAL
ldr r2, =CKEN_DEFAULT
str r2, [r1]
mov pc, lr
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
INITPLATFORM
mov pc, lr
LTORG ; Insert a literal pool here
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;; Processor IDs used for FFUART Transmissions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ALIGN
BANNER DCB 0xA, 0xD, 0xA, 0xD, "*****88888888**Beginning System Initialization*******", 0xA, 0xD, 0
IF DALHART = "1"
ALIGN
A1_CTLA_BNR DCB 0xA, 0xD, " CPU ID = A1 PXA26x", 0xA, 0xD, 0
ALIGN
B0_CTLA_BNR DCB 0xA, 0xD, " CPU ID = B0 PXA26x", 0xA, 0xD, 0
ALIGN
B1_CTLA_BNR DCB 0xA, 0xD, " CPU ID = B1 PXA26x", 0xA, 0xD, 0
ALIGN
B2_CTLA_BNR DCB 0xA, 0xD, " CPU ID = B2 PXA26x", 0xA, 0xD, 0
ALIGN
C0_CTLA_BNR DCB 0xA, 0xD, " CPU ID = C0 PXA26x", 0xA, 0xD, 0
ELSE
ALIGN
A1_CTLA_BNR DCB 0xA, 0xD, " CPU ID = A1 PXA250", 0xA, 0xD, 0
ALIGN
B0_CTLA_BNR DCB 0xA, 0xD, " CPU ID = B0 PXA250", 0xA, 0xD, 0
ALIGN
B1_CTLA_BNR DCB 0xA, 0xD, " CPU ID = B1 PXA250", 0xA, 0xD, 0
ALIGN
B2_CTLA_BNR DCB 0xA, 0xD, " CPU ID = B2 PXA250", 0xA, 0xD, 0
ALIGN
C0_CTLA_BNR DCB 0xA, 0xD, " CPU ID = C0 PXA250", 0xA, 0xD, 0
ENDIF
ALIGN
A1_SBNL_BNR DCB 0xA, 0xD, " CPU ID = A1 PXA210", 0xA, 0xD, 0
ALIGN
B0_SBNL_BNR DCB 0xA, 0xD, " CPU ID = B0 PXA210", 0xA, 0xD, 0
ALIGN
B1_SBNL_BNR DCB 0xA, 0xD, " CPU ID = B1 PXA210", 0xA, 0xD, 0
ALIGN
B2_SBNL_BNR DCB 0xA, 0xD, " CPU ID = B2 PXA210", 0xA, 0xD, 0
ALIGN
C0_SBNL_BNR DCB 0xA, 0xD, " CPU ID = C0 PXA210", 0xA, 0xD, 0
ALIGN
SOFT_RST_STR DCB 0xA, 0xD, " Got Soft Reset", 0xA, 0xD, 0
ALIGN
SLEEP_RST_STR DCB 0xA, 0xD, " Got Sleep Reset", 0xA, 0xD, 0
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
DISPLAY_FREQS
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;; DISPLAY FREQUENCY SETTINGS ;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Load the CPU ID value into R9 for future use
;
mrc p15, 0, r9, c0, c0, 0 ; Grab CPU ID again for banners
;
; Tx a banner
;
ldr r1, =FFUART_BASE_PHYSICAL
InitFFUART r1, r2, r3
add r2, pc, #BANNER-(.+8)
PrintStr r1, r2, r3 ; Tx a simple Banner
;
; Tx the Processor stepping
;
ldr r4, =COTULLA_CP15_A1_VAL ;load R4 with value
cmp r9, r4 ;Compare
addeq r2, pc, #A1_CTLA_BNR-(.+8) ;Running A1 Cotulla
beq %F5 ;Transmit
ldr r4, =COTULLA_CP15_B0_VAL ;load R4 with value
cmp r9, r4 ;Compare
addeq r2, pc, #B0_CTLA_BNR-(.+8) ;Running B0 Cotulla
beq %F5 ;Tranmit
ldr r4, =COTULLA_CP15_B1_VAL ;load R4 with value
cmp r9, r4 ;Compare
addeq r2, pc, #B1_CTLA_BNR-(.+8) ;Running B1 Cotulla
beq %F5 ;Transmit
ldr r4, =COTULLA_CP15_B2_VAL ;load R4 with value
cmp r9, r4 ;Compare
addeq r2, pc, #B2_CTLA_BNR-(.+8) ;Running B2 Cotulla
beq %F5 ;Transmit
ldr r4, =COTULLA_CP15_C0_VAL ;load R4 with value
cmp r9, r4 ;Compare
addeq r2, pc, #C0_CTLA_BNR-(.+8) ;Running C0 Cotulla
beq %F5 ;Transmit
ldr r4, =SABINAL_CP15_A1_VAL ;load R4 with value
cmp r9, r4 ;Compare
addeq r2, pc, #A1_SBNL_BNR-(.+8) ;Running A1 Sabinal
beq %F5 ;Transmit
ldr r4, =SABINAL_CP15_B0_VAL ;load R4 with value
cmp r9, r4 ;Compare
addeq r2, pc, #B0_SBNL_BNR-(.+8) ;Running B0 Sabinal
beq %F5 ;Tranmit
ldr r4, =SABINAL_CP15_B1_VAL ;load R4 with value
cmp r9, r4 ;Compare
addeq r2, pc, #B1_SBNL_BNR-(.+8) ;Running B1 Sabinal
beq %F5 ;Transmit
ldr r4, =SABINAL_CP15_B2_VAL ;load R4 with value
cmp r9, r4 ;Compare
addeq r2, pc, #B2_SBNL_BNR-(.+8) ;Running B2 Sabinal
beq %F5 ;Transmit
ldr r4, =SABINAL_CP15_C0_VAL ;load R4 with value
cmp r9, r4 ;Compare
addeq r2, pc, #C0_SBNL_BNR-(.+8) ;Running B2 Sabinal
beq %F5 ;Transmit
5
ldr r1, =FFUART_BASE_PHYSICAL ; Tx Processor Stepping
PrintStr r1, r2, r3
;
;Banner the SDCLK[1] setting
;
ldr r1, =MDREFR_BASE_PHYSICAL
ldr r2, [r1] ; read MDREFR
ands r2, r2, #0x20000 ; check K1DB2
addne r2, pc, #SDCLK_HALF_MSG-(.+8) ; K1DB2 SET (run SDCLK= .5(MemClk))
addeq r2, pc, #SDCLK_EQU_MSG-(.+8) ; K1DB2 CLEAR (run SDCLK= MemClk)
ldr r1, =FFUART_BASE_PHYSICAL
PrintStr r1, r2, r3 ; Tx the setting
;
; Next, Tx the Turbo/Run/MemClk settings
;
ldr r3, =CCCR_BASE_PHYSICAL
GET_CCCR r0, r3, r2 ; r0 gets the value in CCCR
;
; First, decode the 'L' parameter
;
and r0, r0, #0x1F ; extract 'L'
cmp r0, #0x1 ; L='00001' = 27
addeq r2, pc, #L_27-(.+8)
beq %F10
cmp r0, #0x2 ; L='00010' = 32
addeq r2, pc, #L_32-(.+8)
beq %F10
cmp r0, #0x3 ; L='00011' = 36
addeq r2, pc, #L_36-(.+8)
beq %F10
cmp r0, #0x4 ; L='00100' = 40
addeq r2, pc, #L_40-(.+8)
beq %F10
cmp r0, #0x5 ; L='00101' = 45
addeq r2, pc, #L_45-(.+8)
beq %F10
cmp r0, #0x1F ; L='11111' = 9
addeq r2, pc, #L_09-(.+8)
10
ldr r1, =FFUART_BASE_PHYSICAL ; Tx the 'L' setting
PrintStr r1, r2, r3
;
; Next, decode the 'M' parameter
;
ldr r3, =CCCR_BASE_PHYSICAL
GET_CCCR r0, r3, r2 ; r0 gets the value in CCCR
and r0, r0, #0x60 ; extract 'M'
cmp r0, #0x20 ; M='01' = 1
addeq r2, pc, #M_1-(.+8)
beq %F20
cmp r0, #0x40 ; M='10' = 2
addeq r2, pc, #M_2-(.+8)
beq %F20
cmp r0, #0x60 ; M='11' = 3
addeq r2, pc, #M_3-(.+8)
20
ldr r1, =FFUART_BASE_PHYSICAL ; Tx the 'M' setting
PrintStr r1, r2, r3
;
; Now decode the 'N' parameter
;
ldr r3, =CCCR_BASE_PHYSICAL
GET_CCCR r0, r3, r2 ; r0 gets the value in CCCR
and r0, r0, #0x380 ; extract 'N'
cmp r0, #0x100 ; N='010' = 1
addeq r2, pc, #N_1-(.+8)
beq %F30
cmp r0, #0x180 ; N='011' = 1.5
addeq r2, pc, #N_15-(.+8)
beq %F30
cmp r0, #0x200 ; N='100' = 2
addeq r2, pc, #N_2-(.+8)
beq %F30
cmp r0, #0x280 ; N='101' = 2.5
addeq r2, pc, #N_25-(.+8)
beq %F30
cmp r0, #0x300 ; N='110' = 3
addeq r2, pc, #N_3-(.+8)
30
ldr r1, =FFUART_BASE_PHYSICAL ; Tx the setting
PrintStr r1, r2, r3
;
; Finally, display S24 (dot=Run, !dot=Turbo)
;
GET_CLKCFG r0 ; cp14.6[3:0] in r0
ands r0, r0, #1
addne r2, pc, #TURBOMODE-(.+8)
addeq r2, pc, #RUNMODE-(.+8)
ldr r1, =FFUART_BASE_PHYSICAL ; Tx the setting
PrintStr r1, r2, r3
; ****************************************************************************
; Scrub SDRAM iff Hard-Reset.
;
; 64MB: Cotulla
; 32MB: Sabinal
;
tst r10, #RCSR_GPIO_RESET
; bne END_DISPLAY
bne Got_GPIO_RESET
tst r10, #RCSR_SLEEP_RESET
bne Got_SLEEP_RESET
; If we're booting a flash image (assuming it's a BIN image), don't scrub RAM otherwise
; we'll erase the contents of the bootargs block which is needed by the OAL.
;
IF _FLASH != "1"
add r2, pc, #START_SCRUBBING-(.+8)
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