📄 fwxsc1.s.bak
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; write back mdrefr
;
str r4, [r1, #MDREFR_OFFSET]
ldr r4, [r1, #MDREFR_OFFSET]
; deassert SLFRSH
;
bic r4, r4, #0x00400000
; write back mdrefr
;
str r4, [r1, #MDREFR_OFFSET]
; assert E1PIN
;
orr r4, r4, #0x00008000
; write back mdrefr
;
str r4, [r1, #MDREFR_OFFSET]
ldr r4, [r1, #MDREFR_OFFSET]
nop
nop
; ****************************************************************************
; Step 4
;
; fetch platform value of mdcnfg
;
ldr r2, =MDCNFG_VAL ; 64 MB, SA-1111 compat. mode
; disable all sdram banks
;
bic r2, r2, #(MDCNFG_DE0 :OR: MDCNFG_DE1)
bic r2, r2, #(MDCNFG_DE2 :OR: MDCNFG_DE3)
bic r2, r2, #MDCNFG_DWID0 ; 0: 32-bit
; write initial value of mdcnfg, w/o enabling sdram banks
;
;// by cdamo str r2, [r1, #MDCNFG_OFFSET]
; ****************************************************************************
; Step 5
;
; pause for 200 uSecs
;
ldr r3, =OSCR_BASE_PHYSICAL ; reset the OS Timer Count to zero
mov r2, #0
str r2, [r3]
ldr r4, =0x300 ; really 0x2E1 is about 200usec, so 0x300 should be plenty
10
ldr r2, [r3]
cmp r4, r2
bgt %B10
; ****************************************************************************
; Step 6
;
mov r0, #0x78 ; turn everything off
mcr p15, 0, r0, c1, c0, 0 ; (caches off, MMU off, etc.)
; ****************************************************************************
; Step 7
;
; Access memory *not yet enabled* for CBR refresh cycles (8)
; - CBR is generated for all banks
ldr r2, =SDRAM_BASE_PHYSICAL
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
; Fix for erratum #116. Need to make up for ineffective first mem access.
str r2, [r2]
; ****************************************************************************
; Step 8: NOP (enable dcache if you wanna... we dont)
;
; ****************************************************************************
; Step 9
;
; get memory controller base address
;
ldr r1, =MEMC_BASE_PHYSICAL
; fetch current mdcnfg value
;
ldr r3, [r1, #MDCNFG_OFFSET]
; enable sdram bank 0 if installed (must do for any populated bank)
;
orr r3, r3, #MDCNFG_DE0
; write back mdcnfg, enabling the sdram bank(s)
;
str r3, [r1, #MDCNFG_OFFSET]
; ****************************************************************************
; Step 10
;
; write mdmrs
;
ldr r2, =MDMRS_VAL
str r2, [r1, #MDMRS_OFFSET]
; ****************************************************************************
; Step 11: Final Step
;
IF 0=1 ; do not enable APD. MEMC issuing excessive refreshes when set.
; * A1 Errata #5: Do not enable APD here, since I will be doing
; a frequency change later. Doing so will hang the MEMC state machine.
;
ldr r3, [r1, #MDREFR_OFFSET]
; enable auto-power down
;
orr r3, r3, #MDREFR_APD
; write back mdrefr
;
str r3, [r1, #MDREFR_OFFSET]
ENDIF
INITMEMC_Got_GPIO_RESET
mov pc, lr
;;
;; End of INITMEMC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
INITINTC
; ********************************************************************
; Disable (mask) all interrupts at the interrupt controller
;
; clear the interrupt level register (use IRQ, not FIQ)
;
mov r1, #0
ldr r2, =ICLR_BASE_PHYSICAL
str r1, [r2]
; mask all interrupts at the controller
;
ldr r2, =ICMR_BASE_PHYSICAL
str r1, [r2]
mov pc, lr
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
INITCLKS
; ********************************************************************
; Disable the peripheral clocks, and set the core clock
; frequency.
;
; Turn Off ALL on-chip peripheral clocks for re-configuration
; *Note: See label 'ENABLECLKS' for the re-enabling
;
ldr r1, =CKEN_BASE_PHYSICAL
mov r2, #0
str r2, [r1]
; If Sleep or GPIO Reset, we don't need to re-init the Clocks
; *However, I DO need to restore cp14 when waking.
;
; **BMAN: for now, we will reset cp14... will eventually rip the desired value from the sleep structure
;
;tst r10, #RCSR_SLEEP_RESET:OR:RCSR_GPIO_RESET
;bne INITOST
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Lubbock: Allow the user to select the {T/R/M} with predetermined
; SDCLK. Based on Table 3-1 in PXA250 and PXA210 Dev Man.
;
; * = Must set MDREFR.K1DB2 to halve the MemClk for desired SDCLK[1]
;
; S25, S26 used to provide all 400 MHz BIN values for Cotulla (0,0 - 1,3)
; S25, S26 used to provide all 200 MHz BIN values for Sabinal
;
; S23: Force the halving of MemClk when deriving SDCLK[1]
; DOT: no override !DOT: halve (if not already forced half)
; *For certain MemClks, SDCLK's derivation is forced to be halved
;
; S24: Run/Turbo.
; DOT: Run mode !DOT: Turbo mode
;
;
; Sandgate OR invalid Rotary selection: default to {200/200/100}
;
; ldr r2, =(CCCR_L27 :OR: CCCR_M2 :OR: CCCR_N10) ; DEFAULT: {200/200/100}
ldr r2, =(CCCR_L27 :OR: CCCR_M4 :OR: CCCR_N10)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;
; Preload r4 for the workaround located just below the next section
ldr r4, =B0_STEPPING ;Preload R4 for Comparison located after the next IF section
; ... and write the core clock config register
;
ldr r1, =CCCR_BASE_PHYSICAL
str r2, [r1]
;...IF :LNOT: :DEF: B0_Cotulla
cmp r9, r4 ; R4 should've been preloaded just before the above IF section with B0 VAL
beq OSCC_OON_DONE ; If we're not running on B0 silicon, skip this work around
; ~~~B0 errata: 32K OSC not functional~~~
; enable the 32Khz oscillator for RTC and PowerManager
;
ldr r1, =OSCC_BASE_PHYSICAL
mov r2, #OSCC_OON
str r2, [r1]
; **
; **NOTE: Spin here until OSCC.OOK get set,
; meaning the 32KHz PLL has settled.
; **
60
ldr r2, [r1]
ands r2, r2, #1
beq %B60
;... ENDIF ; B0_COTULLA
OSCC_OON_DONE
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; initiate the frequency change sequence
;
; Lubbock: Allow the user to choose whether to run in Run Mode or Turbo Mode
; via dip S24:
;
; DOT: Run
; noDOT: Turbo
;
mov r1, #2 ; frequency change bit
;;;;;;;;;;;;;;;
;PRELOAD r3 with A1 value for upcoming compare (down a few lines)
ldr r3, =A1_STEPPING
mcr p14, 0, r1, c6, c0, 0 ; write CCLKCFG
; ;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;... IF :DEF: A1_Cotulla !Also for A1_Sabinal! - we account for by looking only @ stepping val
; Check to see if we are running A1 silicon
; r3 preloaded above (just before writing CCLKCFG)
cmp r9, r3
; ****************************************************************************
; !!! Take care of A1 Errata Sighting #4 --
; after a frequency change, the memory controller must be restarted
;
; get memory controller base address
ldreq r1, =MEMC_BASE_PHYSICAL
; get the current state of MDREFR
;
ldreq r2, [r1, #MDREFR_OFFSET]
; clear E0PIN, E1PIN
;
biceq r3, r2, #(MDREFR_E0PIN :OR: MDREFR_E1PIN)
; write MDREFR with E0PIN, E1PIN cleared (disable sdclk[0,1])
;
streq r3, [r1, #MDREFR_OFFSET]
; then write MDREFR with E0PIN, E1PIN set (enable sdclk[0,1])
;
streq r2, [r1, #MDREFR_OFFSET]
; get the current state of MDCNFG
;
ldreq r3, [r1, #MDCNFG_OFFSET]
; disable all SDRAM banks
;
biceq r3, r3, #(MDCNFG_DE0 :OR: MDCNFG_DE1)
biceq r3, r3, #(MDCNFG_DE2 :OR: MDCNFG_DE3)
; write back MDCNFG
;
streq r3, [r1, #MDCNFG_OFFSET]
; Access memory not yet enabled for CBR refresh cycles (8)
; - CBR is generated for *all* banks
ldreq r2, =SDRAM_BASE_PHYSICAL
streq r2, [r2]
streq r2, [r2]
streq r2, [r2]
streq r2, [r2]
streq r2, [r2]
streq r2, [r2]
streq r2, [r2]
streq r2, [r2]
; fetch current mdcnfg value
;
ldreq r3, [r1, #MDCNFG_OFFSET]
; enable sdram bank 0 if installed
;
orreq r3, r3, #MDCNFG_DE0
; write back mdcnfg, enabling the sdram bank(s)
;
streq r3, [r1, #MDCNFG_OFFSET]
; write mdmrs
;
ldreq r2, =MDMRS_VAL
streq r2, [r1, #MDMRS_OFFSET]
IF 0=1 ; do not enable APD. MEMC issuing excessive refreshes when set.
; get current value of mdrefr
;
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