📄 fwxsc1.s.bak
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CPWAIT
ldr r0, =0x00000000 ; get a zero to turn things off
mcr p15, 0, r0, c8, c7, 0 ; flush (invalidate) I/D tlb's
mcr p15, 0, r0, c7, c7, 0 ; flush (invalidate) I/D caches
mcr p15, 0, r0, c7, c10, 4 ; Drain the write buffer
nop
nop
nop
mvn r0, #0 ; grant manager access to all domains
mcr p15, 0, r0, c3, c0, 0
; ********************************************************************
; Read & Init Reset Cause bits in RCSR.
;
ldr r0, =RCSR_BASE_PHYSICAL
ldr r10, [r0]
; extract the reset cause bits
;
mov r2, #RCSR_ALL ; Mask RCSR (read lower byte only)
and r10, r10, r2 ; r10 now holds the conditioned Reset Reason
; clear the reset cause bits (they're sticky)
;
str r2, [r0]
; ********************************************************************
; Read and store PSSR, too - it will be reset later, after GPIOs are initialized.
; Unclear when we'll need this information, but don't throw a good status away.
;
ldr r0, =PSSR_BASE_PHYSICAL
ldr r12, [r0]
; extract the reset cause bits
;
mov r2, #PSSR_VALID_MASK ; Mask PSSR (All in lower byte)
and r12, r12, r2 ; r12 now holds the conditioned PSSR
mov r12, r12, lsl #16 ; Move to upper half of register
orr r10, r10, r12 ; R10 now has RCSR in lower half and PSSR in upper.
; ********************************************************************
; Reasons for being here: 1) Hard Reset 2) Wake from Sleep 3) GPIO Reset 4) Watchdog Reset 5) Eboot Handoff
;
;
; If Sleep_Reset: reinit all but RTC, PWRMAN, CLKS (except cp14)... so reinit: OST, INTC, GPIO
; If GPIO_Reset: reinit all but MEMC.Config, RTC, CLKS (except cp14)... so reinit: treat like sleep
; If Watchdog_Reset: reinit all but RTC.RTTR, CLK.OSCC... so reinit: treat like a hard reset, minus OSCC and RTTR init.
; If Hard_Reset: reinit all
;
; // IF (Sleep_Reset OR GPIO_Reset OR Watchdog_Reset OR Hard_Reset) goto InitMemC
; // else goto InitMMU
;
;tst r10, #RCSR_SLEEP_RESET:OR:RCSR_HARD_RESET:OR:RCSR_WDOG_RESET:OR:RCSR_GPIO_RESET
; ********************************************************************
; TODO: readthe SCR and stash vital info into the scratchpad reg
;
mov pc, lr
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
INITGPIO
; ********************************************************************
; Set Alternate Functions:
;
; First, Set GPSRx,y,z HIGH for active low outputs...
;
ldr r1, =GPSR_x_BASE_PHYSICAL
ldr r2, =GPSRx_DEFA_VAL
str r2, [r1]
ldr r1, =GPSR_y_BASE_PHYSICAL
ldr r2, =GPSRy_DEFA_VAL
str r2, [r1]
ldr r1, =GPSR_z_BASE_PHYSICAL
ldr r2, =GPSRz_DEFA_VAL
str r2, [r1]
; ...then Set GPCR LOW for active high outputs
;
ldr r1, =GPCR_x_BASE_PHYSICAL
ldr r2, =GPCRx_DEFA_VAL
str r2, [r1]
ldr r1, =GPCR_y_BASE_PHYSICAL
ldr r2, =GPCRy_DEFA_VAL
str r2, [r1]
ldr r1, =GPCR_z_BASE_PHYSICAL
ldr r2, =GPCRz_DEFA_VAL
str r2, [r1]
; Next, Set GPDR accordingly for all pins
;
ldr r1, =GPDR_x_BASE_PHYSICAL
ldr r2, =GPDRx_DEFA_VAL
str r2, [r1]
ldr r1, =GPDR_y_BASE_PHYSICAL
ldr r2, =GPDRy_DEFA_VAL
str r2, [r1]
ldr r1, =GPDR_z_BASE_PHYSICAL
ldr r2, =GPDRz_DEFA_VAL
str r2, [r1]
; Finally, set GAFR0,1 for alternate functions
;
ldr r1, =GAFR0_x_BASE_PHYSICAL
ldr r2, =GAFR0x_DEFA_VAL
str r2, [r1]
ldr r1, =GAFR1_x_BASE_PHYSICAL
ldr r2, =GAFR1x_DEFA_VAL
str r2, [r1]
ldr r1, =GAFR0_y_BASE_PHYSICAL
ldr r2, =GAFR0y_DEFA_VAL
str r2, [r1]
ldr r1, =GAFR1_y_BASE_PHYSICAL
ldr r2, =GAFR1y_DEFA_VAL
str r2, [r1]
ldr r1, =GAFR0_z_BASE_PHYSICAL
ldr r2, =GAFR0z_DEFA_VAL
str r2, [r1]
ldr r1, =GAFR1_z_BASE_PHYSICAL
ldr r2, =GAFR1z_DEFA_VAL
str r2, [r1]
; Next, set-to-clear the RDH bit in the PSSR
; to allow GPIO's configged as inputs to function
;
ldr r0, =PSSR_BASE_PHYSICAL
ldr r1, =0x30
str r1, [r0]
IF PLAT_LUBBOCK = "1"
ldr r3, =MSC1_BASE_PHYSICAL ; low - bank 2 Lubbock Registers / SRAM
ldr r2, =0x3FF93FF9 ;//Modify by VICTOR from 0x3FF4A441 ; high - bank 3 Ethernet Controller
str r2, [r3] ; need to set MSC1 before trying to write to the HEX LEDs
ldr r2, [r3] ; need to read it back to make sure the value latches (see MSC section of manual)
ENDIF ; plat_lubbock
mov pc, lr
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALIGN
INITMEMC
; ********************************************************************
; Initlialize Memory Controller
; The sequence below is based on the recommended init steps detailed
; in the EAS, chapter 5.
;
; pause for 200 uSecs- allow internal clocks to settle
; *Note: only need this if hard reset... doing it anyway for now
;
;---- Wait 200 usec
ldr r3, =OSCR_BASE_PHYSICAL ; reset the OS Timer Count to zero
mov r2, #0
str r2, [r3]
ldr r4, =0x300 ; really 0x2E1 is about 200usec, so 0x300 should be plenty
10
ldr r2, [r3]
cmp r4, r2
bgt %B10
; **************************************************** START ROD CODE ************************
; get memory controller base address
ldr r1, =MEMC_BASE_PHYSICAL
; ****************************************************************************
; Step 1
;
; write msc0, read back to ensure data latches
;
ldr r2, =MSC0_VAL
str r2, [r1, #MSC0_OFFSET]
ldr r2, [r1, #MSC0_OFFSET]
IF PLAT_LUBBOCK = "1"
; write msc1
; Sandgate: this causes BCR writes to die!!!!!!!!
ldr r2, =MSC1_VAL
str r2, [r1, #MSC1_OFFSET]
ldr r2, [r1, #MSC1_OFFSET]
ENDIF
; write msc2
ldr r2, =MSC2_VAL
str r2, [r1, #MSC2_OFFSET]
ldr r2, [r1, #MSC2_OFFSET]
; write mecr
ldr r2, =MECR_VAL
str r2, [r1, #MECR_OFFSET]
; write mcmem0
ldr r2, =MCMEM0_VAL
str r2, [r1, #MCMEM0_OFFSET]
; write mcmem1
ldr r2, =MCMEM1_VAL
str r2, [r1, #MCMEM1_OFFSET]
; write mcatt0
ldr r2, =MCATT0_VAL
str r2, [r1, #MCATT0_OFFSET]
; write mcatt1
ldr r2, =MCATT1_VAL
str r2, [r1, #MCATT1_OFFSET]
; write mcio0
ldr r2, =MCIO0_VAL
str r2, [r1, #MCIO0_OFFSET]
; write mcio1
ldr r2, =MCIO1_VAL
str r2, [r1, #MCIO1_OFFSET]
; fly-by-dma is defeatured on this part
; write flycnfg
;ldr r2, =FLYCNFG_SETTINGS
;str r2, [r1, #FLYCNFG_OFFSET]
;-------------------------------------------------------
; 3rd bullet, Step 1
;
; get the mdrefr settings
ldr r3, =MDREFR_VAL
; extract DRI field (we need a valid DRI field)
;
ldr r2, =0xFFF
; valid DRI field in r3
;
and r3, r3, r2
; get the reset state of MDREFR
;
ldr r4, [r1, #MDREFR_OFFSET]
; clear the DRI field
;
bic r4, r4, r2
; insert the valid DRI field loaded above
;
orr r4, r4, r3
; write back mdrefr
;
str r4, [r1, #MDREFR_OFFSET]
; *Note: preserve the mdrefr value in r4 *
; ****************************************************************************
; Step 2
;
; fetch sxcnfg value
;
;ldr r2, =0
; write back sxcnfg
;str r2, [r1, #SXCNFG_OFFSET]
; if sxcnfg=0, don't program for synch-static memory
;cmp r2, #0
;beq %F11
; program sxmrs
;ldr r2, =SXMRS_SETTINGS
;str r2, [r1, #SXMRS_OFFSET]
;11
; ****************************************************************************
; Step 3
;
; Assumes previous mdrefr value in r4, if not then read current mdrefr
; clear the free-running clock bits
; (clear K0Free, K1Free, K2Free
;
bic r4, r4, #(0x00800000 :OR: 0x01000000 :OR: 0x02000000)
; set K1RUN if bank 0 installed
;
orr r4, r4, #0x00010000
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Lubbock: Allow the user to select the {T/R/M} with predetermined
; SDCLK. Based on Table 3-1 in PXA250 and PXA210 Dev Man.
;
; * = Must set MDREFR.K1DB2 to halve the MemClk for desired SDCLK[1]
;
; S25, S26 used to provide all 400 MHz BIN values for Cotulla (0,0 - 1,3)
; S25, S26 used to provide all 200 MHz BIN values for Sabinal
;
; S23: Force the halving of MemClk when deriving SDCLK[1]
; DOT: no override !DOT: halve (if not already forced half)
; *For certain MemClks, SDCLK's derivation is forced to be halved
;
; S24: Run/Turbo.
; DOT: Run mode !DOT: Turbo mode
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Sandgate: SDCLK[1] = MemClk by default
;
IF PLAT_LUBBOCK = "1"
; orreq r4, r4, #0x00020000 ; SDClk[1] = MemClk/2
bicne r4, r4, #0x00020000 ; SDClk[1] = MemClk
ENDIF
; ;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; In GPIO reset, Config registers are preserved and the SDRAM refresh continued.
; So don't step on that.
tst r10, #RCSR_GPIO_RESET
bne INITMEMC_Got_GPIO_RESET
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