fwxsc1.s.bak

在ADS环境下LCD 测试例子

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
; 
; Logic at end of INITMMU needs to be changed to enable waking from sleep under EBOOT.
;
; Copyright ?2000-2002 Intel Corp. 
;
;++
;
; Copyright (c) 1997  Microsoft Corporation
;
; Module Name:
;
;    fwXsc1.s        SABINAL Note: Contains ALL mods.
;
; Abstract:
;
;    This module implements the code necessary to initialize the HW and
;    Kernel interface routines.
;
;
;  Register Useage:  r10 is used to hold the contents of the RCSR throughout this module.
;                      The rest of the registers are fair game.
;
;
;--
    ;OPT    2   ; disable listing
    INCLUDE kxarm.h
    INCLUDE oalintra.inc
    INCLUDE xsc1.inc
    INCLUDE XSC1bd.inc
    INCLUDE fwXsc1.inc    
    INCLUDE sa11x1.inc


    OPT 1   ; reenable listing
    ;OPT    128 ; disable listing of macro expansions
    
    
EBOOT_PARTITION_PHY_BASE        EQU     SDRAM_PHY_EBOOT_PARTITION
EBOOT_PARTITION_VIR_C_BASE      EQU     SDRAM_VIR_C_EBOOT_PARTITION
    
PSFS_BIT_MASK EQU 0x20  ; in cp7, reg 4: (1<<5)

    IF :LNOT: :DEF: ETHBOOT     ; see eboot\fwp2.s
     IMPORT KernelStart         ; If using module as CE Bringup (i.e. Eboot handoff)
    ELSE
     IMPORT  Main               ; If using module as POR init code
    ENDIF


; ----------------------------------------------------------------------------
; ----------------------------------------------------------------------------

    IF :DEF: ETHBOOT
;FW_EXECUTING_FROM_FLASH EQU 1
;    ELSE
;    IF _FLASH = "1"
;FW_EXECUTING_FROM_FLASH EQU 1
 ;       ENDIF
    ENDIF


;************************************************************************
;   StartUp() is the entry point on Reset (all forms of Reset)
;
;   Desription:  StartUp is the first routine executed when powering on
;       the system.  It is also executed first after all forms of XScale
;       resets.  In addition, it is executed after EBOOT has completed
;       downloading the kernel image.  Therefore, this code is shared
;       between EBOOT and the CE Kernel.  The flag 'ETHBOOT' denotes
;       if the code is built for EBOOT or CE Kernel initialization.
;
;       Regardless of the build type, we disable the MMU and caches
;       immediately and flush'em.
;
;       This routine includes all of the necessary board and core-level
;       initialization code to get both Sandgate and Lubbock up.
;
;
;************************************************************************

    EXPORT Reset_Handler
    EXPORT Undefined_Handler
    EXPORT SWI_Handler
    EXPORT Prefetch_Handler
    EXPORT Abort_Handler
    EXPORT IRQ_Handler
    EXPORT FIQ_Handler


    STARTUPTEXT
    LEAF_ENTRY StartUp
   	AREA  Init,CODE
   	ENTRY
start



; --- Setup interrupt / exception vectors
    b Reset_Handler
    b Undefined_Handler
    b SWI_Handler
    b Prefetch_Handler
    b Abort_Handler
    NOP         ; Reserved Vector
    b IRQ_Handler
    b FIQ_Handler       ; May comment out and save a branch


; **********************************
Undefined_Handler


UDEF_STAY        
        b UDEF_STAY
; **********************************


SWI_Handler

SWI_STAY    
        b SWI_STAY
; **********************************


Prefetch_Handler

PRE_STAY    
        b PRE_STAY
; **********************************


Abort_Handler
    ; Note not saving state here.  If data abort before MMU enabled, unrecoverable

   IF B_STEP_PXA2X0 = "1"
   ; Only do this for B steppings of the PXA250 or PXA210 
    mrc     p15, 0, r3, c15, c1, 0   ;Get Reg15 of CP15 for Access to CP7
    orr     r2, r3, #0x080           ; Permission to check CP7
    mcr     p15, 0, r2, c15, c1, 0   ;Now set the value back into R15 of CP15
    CPWAIT  

    mrc     p7,0,r2,c4,c1,0     ; CP7, r4 data into processor r2
    CPWAIT  

    mrc     p15, 0, r3, c15, c1, 0   ;Restore previous permissions mask

    tst     r2, #PSFS_BIT_MASK  ; Power emergency?
    bne     Batt_FaultHandler

    ; Not power emergency.  Don't sleep, just hang.
   ENDIF; B_STEP_PXA2X0 = "1"


ABT_STAY    
        b ABT_STAY
; **********************************


IRQ_Handler
    IF PLAT_LUBBOCK = "1"
        ldr     r1, =0xABCDEFAB
        ldr     r2,  =0x08000010
        str     r1,  [r2]
       
    ENDIF        
        b IRQ_Handler
; **********************************


FIQ_Handler
;=================================change============
   
;FIQ_STAY    
;        b FIQ_STAY
; **********************************



        ; ********************************************************************
        ;  Entry Point on RESET
        ; Put any nearby literals here, get them out of the
  LTORG ; time-critical path
  ALIGN 32
Reset_Handler
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;;  Workaround for early termination of SDRAM autorefresh on exit from 
;;   processor's sleep state in B1 stepping of XPA250/210. (sighting 27004) 
;;   Need first forced refresh within 8 usec.
;;
;;  - Code snippet received from validation team, slightly modified
;;
;;  Notes: - MMU assumed to be inactive at this time, so use physical addresses
;;         -  Eboot didn't boot on A1 stepping without the leading exclusion,
;;              so the core code must be restricted to B1 only.
;;

 IF :DEF: FW_EXECUTING_FROM_FLASH
   IF B_STEP_PXA2X0 = "1"
    ;  Eboot loads BIN image into RAM, turns off the MMU and then jumps here.
    ;  If we're a RAM image, don't mess with it

    mov     r0, #0x48000000         ; Memory controller base physical addr.
    add     r0, r0, #0x4            ; Add offset of MDREFR

    ; Need to set MDREFR:DRI field to 0 for this to work.  Side effect is
    ;  picking the MEMCLK:SDCLK ratio.  The specified value (0x038FF000)
    ;  sets that ratio as 2:1.  This corresponds to the defaults after reset,
    ;  including sleep reset.

    mov     r1, #0x03800000         
    orr     r1, r1, #0x000FF000     ; VALUE

    str     r1, [r0]                ; STORE

    mov     r0, #0xA0000000         ; SDRAM ADDRESS
    ldr     r1, [r0]                ; CAUSES the first row refresh to all partitions
    
    ldr     r1, [r0]                ; CAUSES the second row refresh to all partitions


    ; (Don't need to set IDAE except in B steppings for PXA250 or PXA210)
    ; Setting up IDAE.  Must always do very soon if doing, because cleared by reset.
    ; Leave r0, r1 and r2 for manual refresh logic
    ; Be clever, not clean.  Every usec counts here.  Avoid literal pool usage to keep 
    ;  the execution flow smooth and fast.
    ;   0x40F00000 :PMCR: Power Manager Control register (physical address)

    mov     r4, #0x40000000         ; Main address section
    orr     r4, r4, #0x00F00000     ; Rest of address
    ;
    ; set the immediate sleep mode on batt/vdd fault
    mov     r3, #3                       ; force Imprecise Data Abort on Fault
    str     r3, [r4]
    ; End setting up IDAE

    mov     r2, #0x2000             ; 8k loop

EARLY_REFRESH_LOOP
    ldr     r1, [r0]                ; CAUSES a row refresh to all partitions
    
    subs    r2, r2, #0x1            
    bpl     EARLY_REFRESH_LOOP      ; while >= 0

  ENDIF ;  B_STEP_PXA2X0 = "1" 
 ENDIF ;:DEF: FW_EXECUTING_FROM_FLASH: Can't execute this code from RAM.

;;
;;  End workaround for early termination of SDRAM autorefresh
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


        bl PREINIT
    
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;;  Reset_Handler Sleep logic begins here
;;
        ;
        ; Resume logic: If waking, we expect RCSR[2] to be SET
        ;  If so, the first thing to do is crunch a checksum on the sleep structure to 
        ;  ensure we need to treat the rest of the reset as a wake from sleep.  If the
        ;  checksum is invalid, we should treat the wake as if a hard-reset has occured.
        ;
        ;  Things I don't need to restore: 1)RTC, 2)Power Manager, 3)Clocks (!except cp14!)
        ;
    

;            PHYS_HEX_DISP_CONSTANT 0x99990000,  0x10000000 ; uses r0, r1

        tst r10, #RCSR_SLEEP_RESET
        beq ResetNotSleep   ;  Not sleep. 

        bl INITGPIO    
        bl INITMEMC

            ;; NOTE: GPIO reset and sleep-mediated soft reset require the 
            ;;       same handling.  So sleep-based soft reset will return,
            ;;       but with #RCSR_GPIO_RESET forced in r10

                                       ; For sleep, hopefully go to restoration and never return.
        bl ResetTryToWakeFromSleep   ;  but if bad database, come back and start from scratch anyway.
        
    IF :DEF: TEST_STICK_AT_FAILED_RESTORE
ResetFailedSleepRestore

        b ResetFailedSleepRestore ; This lets us see that we tried to restore.
    ENDIF; :DEF: TEST_STICK_AT_FAILED_RESTORE
ResetNotSleep
;;
;;  Reset_Handler Sleep logic ends here
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    IF :LNOT: :DEF: ETHBOOT
    IF _FLASH != "1"
        b INITMMU
    ENDIF        
    ENDIF

        tst     r10, #RCSR_GPIO_RESET
        beq     NOT_GPIO_RESET
        ldr    r3, =(SLEEPDATA_BASE_PHYSICAL+SleepState_SLEEP_TYPE)
        ldr    r1, =(SLEEP_TYPE_ETHDBG_PART_INIT)
        str    r1, [r3]
        
        bl INITGPIO    
        bl INITMEMC  ; use for soft reset
        bl INITINTC    ; use for soft reset
                    ; Turbo vs. non-Turbo needs to be reconfigured,
                    ;   but pass this by for first cut.
        bl INITCLKS    ; use for soft reset
        bl INITOST     ; use for soft reset
;        bl INITRTC     ; skip for soft reset.  Avoid changing the time.
        bl INITPWRMAN  ; use for soft reset, but maybe a problem with init of GPIO1 wakeup.
        bl ENABLECLKS   ; use, need to re-enable startup config
        bl INITPLATFORM ; use for soft reset
               
        bl DISPLAY_FREQS ; use for soft reset
        b  INITMMU

NOT_GPIO_RESET

        bl INITGPIO    
        bl INITMEMC
        bl INITINTC
        bl INITCLKS
        bl INITOST
        bl INITRTC
        bl INITPWRMAN
        bl ENABLECLKS
        bl INITPLATFORM   
                
        bl DISPLAY_FREQS
        b  INITMMU
        
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    ALIGN
PREINIT
        ; ********************************************************************
        ; Set processor into Supervisior mode (SVC) and disable IRQ & FIQ
        ;
        ldr      r0, =(Mode_SVC :OR: NoIntsMask)
        msr      cpsr_c, r0


        ; ********************************************************************
    ; Grab the CPU ID off of CP15, stuff it into Driver Globals
    ;
    mrc     p15, 0, r9, c0, c0, 0              ; Grab CPU ID
    ldr r1, =DRIVER_GLOBALS_CPU_ID_LOCATION    ; Start of driver globals misc section
    str r9,[r1]                                ; store the CPU ID off 
    and r9, r9, #0xF                           ; Grab only the lowest nibble as it's all we care about
    
        ; ********************************************************************
        ; Disable the MMU and gang regardless of why we are here.
        ;
        
        ldr r0, =0x2001                 ; enable access to all coprocessors
        mcr p15, 0, r0, c15, c1, 0        
        CPWAIT

        ldr     r0, =0x00000078         ; get a zero to turn things off (must write bits[6:3] as 1's)
        mcr p15,0,r0,c1,c0,0            ; Turn Off MMU, I&D Caches, WB.