📄 xsc1bd.inc
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;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;----------------------------------------
; Copyright ?2000-2001 Intel Corp.
;
; Assembler logical name header file for XScale Handheld Development Boards
; (i.e. Sandgate and Lubbock)
;----------------------------------------
INCLUDE GPIO.inc
IF :LNOT::DEF: xsc1bd_inc
xsc1bd_inc EQU 1
; If uncommented, this enables GPIO reset if the target system contains
; the boot code (Eboot or a .NB0 file).
; Currently only for Lubbock platform.
; PLAT_GPIO_RESET EQU 1
lCACHED_TO_UNCACHED_OFFSET EQU 0x20000000
; -----------------------------------------------------------------------------
; --------------- Lubbock Section ---------------------------------------------
; -----------------------------------------------------------------------------
IF PLAT_LUBBOCK = "1"
;
; Lubbock: Boot ROM (flash)
;
BOOT_FLASH_BASE_PHYSICAL EQU 0x00000000
BOOT_FLASH_BASE_C_VIRTUAL EQU 0x98300000
BOOT_FLASH_BASE_U_VIRTUAL EQU (BOOT_FLASH_BASE_C_VIRTUAL + lCACHED_TO_UNCACHED_OFFSET)
; Lubbock: Ethernet (SMC) *Note: Doc seems to sugest this is for the expansion card, but i expect to see on-board
;
SMSC_LAN91C113_BASE_PHYSICAL EQU 0x0c000000
SMSC_LAN91C113_BASE_C_VIRTUAL EQU 0x9F500000
SMSC_LAN91C113_BASE_U_VIRTUAL EQU (SMSC_LAN91C113_BASE_C_VIRTUAL + lCACHED_TO_UNCACHED_OFFSET)
;
; Lubbock:
; Do not have any information on the XDC (i.e. if it will
; be Neponset I, II, or what.)
;
; SDRAM Settings
;MDCNFG_VAL EQU 0x00001AC9 ; SDRAM Config Reg (CL=3)
MDCNFG_VAL EQU 0x000019C9 ;0x00001AC9 ;0x1b9b1bcf ;0x000019C9 ; SDRAM Config Reg (CL=2)
MDREFR_VAL EQU 0x000BC018 ;0x00018018 ;0x01dff029 ;0x000BC018 ; SDRAM Refresh Reg
MDMRS_VAL EQU 0x00000000 ; SDRAM Mode Reg Set Config Reg
; Static Memory Settings
;
; IF FLASH_WIDTH_16_BIT = "1"
;MSC0_VAL EQU 0x2BD0238B ;for 16-bit Dalhart K3 flash
; ELSE
;MSC0_VAL EQU 0x23F223F2 A ; Static Mem. Control Reg 0
MSC0_VAL EQU 0x4F405AF8 ; Static Mem. Control Reg 0 change by cdamo 2005-09-20
; ENDIF
;MSC0_VAL EQU 0x23D223D2 ;0x3f695af0 ;0x24f224f0
MSC1_VAL EQU 0x3ff93ff9 ;0x3ff97ffc ;0x3FF1A441 ; Static Mem. Control Reg 1
MSC2_VAL EQU 0x7FF17FF1 ;0x3ff97ff9 ;0x3ff93ff9 ;0x7FF17FF1 ; Static Mem. Control Reg 2 - NOT USED
; PCMCIA and CF Interfaces
;
MECR_VAL EQU 0x00000000 ; eXpansion memory (PCMCIA/CF) bus config. reg
MCMEM0_VAL EQU 0x00010504 ; Card I-face Common Mem Space socket 0 timing config ?still TBA
MCMEM1_VAL EQU 0x00010504 ; Card I-face Common Mem Space socket 1 timing config ?still TBA
MCATT0_VAL EQU 0x00010504 ; Card I-face Attribute Space socket 0 timing config ?still TBA
MCATT1_VAL EQU 0x00010504 ; Card I-face Attribute Space socket 1 timing config ?still TBA
MCIO0_VAL EQU 0x00004715 ; Card I-face I/O Space socket 0 timing config ?still TBA
MCIO1_VAL EQU 0x00004715 ; Card I-face I/O Space socket 1 timing config ?still TBA
; Synch. Static Memory
;
SXCNFG_VAL EQU 0x00000000 ; Synch. Static Mem. Config. Reg.
SXMRS_VAL EQU 0x00000000 ; Synch. Static Mem. Mode Register Set Config - NOT USED
SXLCR_VAL EQU 0x00000000 ; Synch. Static Mem. Config. Reg. - NOT USED
FLYCNFG_VAL EQU 0x01FE01FE ; Fly-by-DMA config. reg - NOT USED
;
; [** Lubbock: FPGA Register (BLR) offsets from base address **] These differ from 32-bit mode in that the LSB is shifted right 1
;
IF SABINAL = "1"
;
; 16-bit
;
WHOAMI_OFFSET EQU 0x00 ; r/o
HEXLED_OFFSET EQU 0x08 ; r/w
BLANKLED_OFFSET EQU 0x20 ; r/w
DISCRETELED_OFFSET EQU 0x20 ; r/w
CNFG_SWITCHES_OFFSET EQU 0x28 ; r/o
USER_SWITCHES_OFFSET EQU 0x30 ; r/o
MISC_WR_OFFSET EQU 0x40 ; r/w
MISC_RD_OFFSET EQU 0x48 ; r/o
INT_MASK_OFFSET EQU 0x60 ; r/w
INT_CLEAR_OFFSET EQU 0x68 ; r/w
GP_OFFSET EQU 0x80 ; r/w
ELSE
;
; 32-bit
;
WHOAMI_OFFSET EQU 0x00 ; r/o
HEXLED_OFFSET EQU 0x10 ; r/w
BLANKLED_OFFSET EQU 0x40 ; r/w
DISCRETELED_OFFSET EQU 0x40 ; r/w
CNFG_SWITCHES_OFFSET EQU 0x50 ; r/o
USER_SWITCHES_OFFSET EQU 0x60 ; r/o
MISC_WR_OFFSET EQU 0x80 ; r/w
MISC_RD_OFFSET EQU 0x90 ; r/o
INT_MASK_OFFSET EQU 0xC0 ; r/w
INT_CLEAR_OFFSET EQU 0xD0 ; r/w
GP_OFFSET EQU 0x100 ; r/w
ENDIF
;
; Misc Defs
;
;
; GPIO Defs
;
; Init quasi-floating Lubbock GPIOs as outputs. Per Jim Putnam:
; They need to be configured as outputs at bootup time and left as
; outputs. I think the correct solution is to configure them as
; outputs even before the RDH bit is cleared at bootup time. This
; way you never have a CMOS input floating.
;
; That applies to these GPIOs:
; 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 16, 17, 32
; All these pins have weak pull-ups at hardware reset, so their initial
; output levels will be high. GPIO 8 can be used as an active-low chip
; select, so it is covered by this approach also.
;
GPDRx_DEFA_VAL EQU (0x00008000)
GPDRy_DEFA_VAL EQU (0x00FF0380)
GPDRz_DEFA_VAL EQU (0x0001C000)
GRERx_DEFA_VAL EQU (0x0001C409) ; GPIO Rising-Edge Detect
GRERy_DEFA_VAL EQU (0x00000000)
GRERz_DEFA_VAL EQU (0x00000000)
GFERx_DEFA_VAL EQU (0x00000000) ; GPIO Falling-Edge Detect
GFERy_DEFA_VAL EQU (0x00000000)
GFERz_DEFA_VAL EQU (0x00000000)
; GPIO Alternate Functions
GAFR0x_DEFA_VAL EQU (0x81011000) ;(0x80000000)
GAFR1x_DEFA_VAL EQU (0xA55A8151) ;(0x00000000)
GAFR0y_DEFA_VAL EQU (0x999A9558) ;(0x000a8010)
GAFR1y_DEFA_VAL EQU (0xAAA5AAAA) ;(0x0005aaaa)
GAFR0z_DEFA_VAL EQU (0xAAAAAAAA) ;(0x80000000)
GAFR1z_DEFA_VAL EQU (0x00000002)
; Default for GPIO 13 on Lubbock should be low because it is the memory bus grant pin
; Also default GPIO 3 to low because its only defined use is as an active-high
; output to the optional keypad
GPSRx_DEFA_VAL EQU 0x00008000
GPSRy_DEFA_VAL EQU 0x00FF0384
GPSRz_DEFA_VAL EQU 0x0001C000
GPCRx_DEFA_VAL EQU 0x00000000
GPCRy_DEFA_VAL EQU 0x00000000
GPCRz_DEFA_VAL EQU 0x00000000
ENDIF ; // If PLAT_LUBBOCK
; -----------------------------------------------------------------------------
; -----------------------------------------------------------------------------
;
; Processor stepping Values
;
COTULLA_CP15_A1_VAL EQU (0x69052101)
COTULLA_CP15_B0_VAL EQU (0x69052902)
COTULLA_CP15_B1_VAL EQU (0x69052903)
COTULLA_CP15_B2_VAL EQU (0x69052904)
COTULLA_CP15_C0_VAL EQU (0x69052D05)
COTULLA_JTAG_A1_VAL EQU (0x19264013)
COTULLA_JTAG_B0_VAL EQU (0x29264013)
COTULLA_JTAG_B1_VAL EQU (0x39264013)
COTULLA_JTAG_B2_VAL EQU (0x49264013)
COTULLA_JTAG_C0_VAL EQU (0x59264013)
SABINAL_CP15_A1_VAL EQU (0x69052101)
SABINAL_CP15_B0_VAL EQU (0x69052922)
SABINAL_CP15_B1_VAL EQU (0x69052923)
SABINAL_CP15_B2_VAL EQU (0x69052924)
SABINAL_CP15_C0_VAL EQU (0x69052D25)
SABINAL_JTAG_A1_VAL EQU (0x19264013)
SABINAL_JTAG_B0_VAL EQU (0x2926c013)
SABINAL_JTAG_B1_VAL EQU (0x3926c013)
SABINAL_JTAG_B2_VAL EQU (0x4926C013)
SABINAL_JTAG_C0_VAL EQU (0x5926C013)
A1_STEPPING EQU (0x1)
B0_STEPPING EQU (0x2)
B1_STEPPING EQU (0x3)
B2_STEPPING EQU (0x4)
C0_STEPPING EQU (0x5)
;
; Driver Globals definitions
MEM_BASE_PHYSICAL EQU (0xA3C8D000)
DRIVER_GLOBALS_OFFSET EQU (0x13B000)
TOUCH_GLOBALS_OFFSET EQU (0x0)
PCMCIA_GLOBALS_OFFSET EQU (0x100)
PROFILE_GLOBALS_OFFSET EQU (0x200)
MISC_GLOBALS_OFFSET EQU (0x300)
PMU_GLOBALS_OFFSET EQU (0x400)
AC97_GLOBALS_OFFSET EQU (0x500)
UNINIT_MISC_GLOBALS_OFFSET EQU (0x800)
DBG_ETH_GLOBALS_OFFSET EQU (0x900)
DRIVER_GLOBALS_PHYSICAL EQU (MEM_BASE_PHYSICAL + DRIVER_GLOBALS_OFFSET)
DRIVER_GLOBALS_CPU_ID_LOCATION EQU (DRIVER_GLOBALS_PHYSICAL + UNINIT_MISC_GLOBALS_OFFSET)
; //////////////////////////////////////////////////////////////////////
; This macro compares the CPU ID located in Driver Globals against a given
; CPU ID Value
MACRO
IsA1CPUID $w1, $w2
ldr $w1, =DRIVER_GLOBALS_CPU_ID_LOCATION
ldr $w2, [$w1] ; Start of driver globals misc section
ldr $w1, =COTULLA_CP15_A1_VAL
cmp $w1, $w2
MEND
MACRO
IsB0CPUID $w1, $w2
ldr $w1, =DRIVER_GLOBALS_CPU_ID_LOCATION
ldr $w2, [$w1] ; Start of driver globals misc section
ldr $w1, =COTULLA_CP15_B0_VAL
cmp $w1, $w2
MEND
MACRO
IsB1CPUID $w1, $w2
ldr $w1, =DRIVER_GLOBALS_CPU_ID_LOCATION
ldr $w2, [$w1] ; Start of driver globals misc section
ldr $w1, =COTULLA_CP15_B1_VAL
cmp $w1, $w2
MEND
ENDIF
END
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