lcd.h

在ADS环境下LCD 测试例子

// 2005/09/22 liuzy

#ifndef LCD_H
#define LCD_H

//
// Core Clock Configuration Register
//
#define CCCR					(*(volatile int *)) 0x41300000; 	// Core Clock Configuration registers

//
// LCD Controller Register Definitions, associated data structures and bit macros
//

//
// Lcd controller control register
//
#define LCCR0					(*(volatile int *) 0x44000000) 	// Lcd controller Control Register 0
#define LCCR1					(*(volatile int *) 0x44000004) 	// Lcd controller Control Register 1
#define LCCR2					(*(volatile int *) 0x44000008)		// Lcd controller Control Register 2
#define LCCR3					(*(volatile int *) 0x4400000C)	  // Lcd controller Control Register 3

// Lcd DMA Register
#define FDADR0				(*(volatile int *) 0x44000200)		// Lcd DMA Frame Descriptor Address Registers
#define FDADR1				(*(volatile int *) 0x44000210)		// Lcd DMA Frame Descriptor Address Registers
#define FSADR0				(*(volatile int *) 0x44000204)		// Lcd DMA Frame Source Address Registers
#define FSADR1        (*(volatile int *) 0x44000214)		// Lcd DMA Frame Source Address Registers
#define FIDR0					(*(volatile int *) 0x44000208)   // Lcd Frame ID Registers 0
#define FIDR1					(*(volatile int *) 0x44000218)   // Lcd Frame ID Registers 1
#define LDCMD0				(*(volatile int *) 0x4400020C)   // Lcd DMA Command Registers 0
#define LDCMD1				(*(volatile int *) 0x4400021C)   // Lcd DMA Command Registers 1
#define FBR0					(*(volatile int *) 0x44000020)		// Lcd DMA Frame Branch Registers 0
#define FBR1					(*(volatile int *) 0x44000024)		// Lcd DMA Frame Branch Registers 1

// LCD Controller Status Register
#define LCSR					(*(volatile int *) 0x44000038)		// Lcd Controller Status Register

// LCD Controller Interrupt ID Register (LIIDR)
#define LIIDR					(*(volatile int *) 0x4400003C)		// Lcd Controller Interrupt ID Register

// TMED Register
#define TRGBR					(*(volatile int *) 0x44000040)		// TMED RGB Seed Register
#define TCR						(*(volatile int *) 0x44000044)		// TMED Control Register;

//
// LCD Controller Control Register 0 (LCCR0)
//
#define LCD_ENB		0x00000001
#define LCD_CMS		0x00000002
#define LCD_SDS		0x00000004
#define LCD_LDM		0x00000008
#define LCD_SFM		0x00000010
#define LCD_IUM		0x00000020
#define LCD_EFM		0x00000040
#define LCD_PAS		0x00000080
#define LCD_BLE		0x00000100
#define LCD_DPD		0x00000200
#define LCD_DIS		0x00000400
#define LCD_QDM		0x00000800
#define LCD_PDD(n)	((n) << 12)
#define LCD_BM		0x00100000
#define LCD_OUM		0x00200000

//
// LCD Controller Control Register 1 (LCCR1)
//
#define LCD_PPL(n)	((n))
#define LCD_HSW(n)	((n) << 10)
#define LCD_ELW(n)	((n) << 16)
#define LCD_BLW(n)	((n) << 24)

//
// LCD Controller Control Register 2 (LCCR2)
//
#define LCD_LPP(n)	((n))
#define LCD_VSW(n)	((n) << 10)
#define LCD_EFW(n)	((n) << 16)
#define LCD_BFW(n)	((n) << 24)

//
// LCD Controller Control Register 3 (LCCR3)
//
#define LCD_PCD(n)	((n))
#define LCD_ACB(n)	((n) << 8)
#define LCD_API(n)	((n) << 16)
#define LCD_VSP		0x00100000
#define LCD_HSP		0x00200000
#define LCD_PCP		0x00400000
#define LCD_OEP		0x00800000
#define LCD_BPP(n)	((n) << 24)
#define LCD_DPC		0x08000000

//
// LCD Controller DMA Frame Descriptor Address Registers (FDADRx)
//
#define LCD_FDADR(n)	((n) & 0xFFFFFFF0)

//
// LCD Controller DMA Frame Source Address Registers (FSADRx)
//
#define LCD_FSADR(n)	((n) & 0xFFFFFFF8)

//
// LCD Controller DMA Frame ID Registers (FIDRx)
//
#define LCD_FIDR(n)		((n) & 0xFFFFFFF8)

//
// LCD Controller DMA Command Registers (LDCMDx)
//
#define LCD_Len(n)		((n))
#define LCD_EOFInt		0x00200000
#define LCD_SOFInt		0x00400000
#define LCD_Pal			0x04000000

//
// LCD Controller DMA Frame Branch Registers (FBRx)
//
#define LCD_BRA			0x00000001
#define LCD_BINT		0x00000002
#define LCD_SrcAddr(n)	((n) << 4)

//
// LCD Controller Status Register (LCSR)
//
#define LCD_LDD		0x00000001
#define LCD_SOF		0x00000002
#define LCD_BER		0x00000004
#define LCD_ABC		0x00000008
#define LCD_IUL		0x00000010
#define LCD_IUU		0x00000020
#define LCD_OU		0x00000040
#define LCD_QD		0x00000080
#define LCD_EOF		0x00000100
#define LCD_BS		0x00000200
#define LCD_SINT	0x00000400

//
// LCD Controller TMED RGB Seed Register (TRGBR)
//
#define LCD_TRS(n) ((n))
#define LCD_TGS(n) ((n) << 8)
#define LCD_TBS(n) ((n) << 16)


//
// LCD Controller TMED Control Register (TCR)
//
#define LCD_TM2S	0x00000001
#define LCD_TM1S	0x00000002
#define LCD_TM2En	0x00000004
#define LCD_TM1En	0x00000008
#define LCD_TVBS(n)	((n) << 4)
#define LCD_THBS(n)	((n) << 8)
#define LCD_TSCS(n)	((n) << 12)
#define LCD_TED		0x00004000

#endif // LCD_H

























/*


typedef struct 
{
	unsigned short palette[256];
}LCD_PALETTE;


typedef struct  
{
	unsigned int FDADR;		// Pointer to next frame descriptor (Physical address)
	unsigned int FSADR;		// Pointer to the data (Physical address)
	unsigned int FIDR;		// Frame descriptor ID
	unsigned int LDCMD;		// DMA command
	unsigned int PHYSADDR;  // PHYSADDR contains the physical address of this descriptor.
}LCD_FRAME_DESCRIPTOR;

typedef struct  
{
	unsigned int LCCR0;			// 0x4400 0000
	unsigned int LCCR1;			// 0x4400 0004
	unsigned int LCCR2;			// 0x4400 0008
	unsigned int LCCR3;			// 0x4400 000C
	unsigned int reserved0[4];	// 0x4400 0010
	unsigned int FBR0;			// 0x4400 0020
	unsigned int FBR1;			// 0x4400 0024
	unsigned int reserved1[4];	// 0x4400 0028
	unsigned int LCSR;			// 0x4400 0038
	unsigned int LIIDR;			// 0x4400 003C
	unsigned int TRGBR;			// 0x4400 0040
	unsigned int TCR;			// 0x4400 0044
	unsigned int reserved2[110];// 0x4400 0048
	unsigned int FDADR0;		// 0x4400 0200
	unsigned int FSADR0;		// 0x4400 0204
	unsigned int FIDR0;			// 0x4400 0208
	unsigned int LDCMD0;		// 0x4400 020C
	unsigned int FDADR1;		// 0x4400 0210
	unsigned int FSADR1;		// 0x4400 0214
	unsigned int FIDR1;			// 0x4400 0218
	unsigned int LDCMD1;		// 0x4400 021C
}SA2lcdregs;

#define NUM_FRAME_BUFFERS 2*/




//#define NAND_IO      (*(volatile UCHAR *)) 0x04000000; ???????需要map否?????