📄 fwxsc1.inc
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;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;/***********************************************************************
; * Copyright ?2000-2001 Intel Corp.
;************************************************************************
;
; Assembly language macros & definitions for the Cotulla initialization code.
;
; This is an assembly language include file.
;
;***********************************************************************/
IF :LNOT::DEF: fwxsc1_inc
fwxsc1_inc EQU 1
RCSR_ALL EQU 0xF
Mode_SVC EQU 0x13
Mode_USR EQU 0x10
NoIntsMask EQU 0x000000C0
IRQIntsMask EQU 0x7F ; 0=enabled, 1=disabled
IrqFiqEnable EQU 0xFFFFFF3F
RCSR_HARD_RESET EQU 0x1
RCSR_WDOG_RESET EQU 0x2
RCSR_SLEEP_RESET EQU 0x4
RCSR_GPIO_RESET EQU 0x8
;
; Defs used for Eboot portion of fwxsc1.s
;
EbootOffset EQU 0x00078000 ; comes from BOOT.BIB! Is the offset into EBOOT_PARTITION
EBootImageLen EQU 0x00020000 ; From BOOT.BIB, size field
StackOffset EQU 0x00068000
; val for L, Mem Clk
CCCR_L09 EQU (0x1F) ; * For Sabinal Processors only *
CCCR_L27 EQU (0x1)
CCCR_L32 EQU (0x2)
CCCR_L36 EQU (0x3)
CCCR_L40 EQU (0x4)
CCCR_L45 EQU (0x5)
; field values for M, memory-to-run-mode multiplier
CCCR_M1 EQU (0x1 :SHL: 5)
CCCR_M2 EQU (0x2 :SHL: 5)
CCCR_M4 EQU (0x3 :SHL: 5)
; field values for N, run-mode-to-turbo-mode multiplier
CCCR_N10 EQU (0x2 :SHL: 7) ; N=1.0
CCCR_N15 EQU (0x3 :SHL: 7) ; N=1.5
CCCR_N20 EQU (0x4 :SHL: 7) ; N=2.0
CCCR_N25 EQU (0x5 :SHL: 7) ; N=2.5
CCCR_N30 EQU (0x6 :SHL: 7) ; N=3.0
;
; OSC/Clock Defs
;
PLATFORM_MEMORY EQU CCCR_L27
CORE_CLK_100MHZ EQU (PLATFORM_MEMORY :OR: CCCR_M1 :OR: CCCR_N20)
CORE_CLK_200MHZ EQU (PLATFORM_MEMORY :OR: CCCR_M2 :OR: CCCR_N20)
CORE_CLK_400MHZ EQU (PLATFORM_MEMORY :OR: CCCR_M4 :OR: CCCR_N10)
CORE_CLK_DEFAULT EQU (CORE_CLK_400MHZ)
OSCC_OON EQU 0x00000002
CKEN_DEFAULT EQU 0x000179EF ; All on-chip periphs clocked
BIT0 EQU (1 :SHL: 0)
BIT1 EQU (1 :SHL: 1)
BIT2 EQU (1 :SHL: 2)
BIT3 EQU (1 :SHL: 3)
BIT4 EQU (1 :SHL: 4)
BIT5 EQU (1 :SHL: 5)
BIT6 EQU (1 :SHL: 6)
BIT7 EQU (1 :SHL: 7)
BIT8 EQU (1 :SHL: 8)
BIT9 EQU (1 :SHL: 9)
BIT10 EQU (1 :SHL: 10)
BIT11 EQU (1 :SHL: 11)
BIT12 EQU (1 :SHL: 12)
BIT13 EQU (1 :SHL: 13)
BIT14 EQU (1 :SHL: 14)
BIT15 EQU (1 :SHL: 15)
BIT16 EQU (1 :SHL: 16)
BIT17 EQU (1 :SHL: 17)
BIT18 EQU (1 :SHL: 18)
BIT19 EQU (1 :SHL: 19)
BIT20 EQU (1 :SHL: 20)
BIT21 EQU (1 :SHL: 21)
BIT22 EQU (1 :SHL: 22)
BIT23 EQU (1 :SHL: 23)
BIT24 EQU (1 :SHL: 24)
BIT25 EQU (1 :SHL: 25)
BIT26 EQU (1 :SHL: 26)
BIT27 EQU (1 :SHL: 27)
BIT28 EQU (1 :SHL: 28)
BIT29 EQU (1 :SHL: 29)
BIT30 EQU (1 :SHL: 30)
BIT31 EQU (1 :SHL: 31)
;
; Bits used for Memory Controller Init
;
; register bit masks - mdcnfg
MDCNFG_DE0 EQU (BIT0)
MDCNFG_DE1 EQU (BIT1)
MDCNFG_DWID0 EQU (BIT2)
MDCNFG_DCAC0 EQU (BIT3+BIT4)
MDCNFG_DRAC0 EQU (BIT5+BIT6)
MDCNFG_DNB0 EQU (BIT7)
MDCNFG_DTC0 EQU (BIT8+BIT9)
MDCNFG_DADDR0 EQU (BIT10)
MDCNFG_DLATCH0 EQU (BIT11)
MDCNFG_RESERVED0 EQU (BIT12+BIT13+BIT14+BIT15)
MDCNFG_DE2 EQU (BIT16)
MDCNFG_DE3 EQU (BIT17)
MDCNFG_DWID2 EQU (BIT18)
MDCNFG_DCAC2 EQU (BIT19+BIT20)
MDCNFG_DRAC2 EQU (BIT21+BIT22)
MDCNFG_DNB2 EQU (BIT23)
MDCNFG_DTC2 EQU (BIT24+BIT25)
MDCNFG_DADDR2 EQU (BIT26)
MDCNFG_DLATCH2 EQU (BIT27)
MDCNFG_RESERVED2 EQU (BIT28+BIT29+BIT30+BIT31)
MDREFR_E0PIN EQU 0x00001000
MDREFR_K0RUN EQU 0x00002000
MDREFR_K1RUN EQU 0x00010000
MDREFR_K2RUN EQU 0x00040000
MDREFR_SLFRSH EQU 0x00400000
MDREFR_E1PIN EQU 0x00008000
MDREFR_K1DB2 EQU 0x00020000 ; run SDCLK @ .5(MClk)
MDREFR_APD EQU 0x00100000
BANK_SHIFT EQU 20
;
; Bits used for Power Manager
;
PCFR_OPDE EQU 0x00000001
PCFR_FP EQU 0x00000002
PCFR_FS EQU 0x00000004
PCFR_DS EQU 0x00000008
PWER_WE0 EQU 0x00000001
PWER_WE1 EQU 0x00000002
PWER_WERTC EQU 0x80000000
;
; Bits used for the HWConfig Reg (aka PowerManager.ScratchPad)
;
HWConfig_RESET EQU (0x1 :SHL: 0)
HWCONFIG_DEFAULT EQU 0x01155046
HWConfig_BootromPM EQU (0x1 :SHL: 12)
PAGEMODE_ON EQU (0x1)
;
; Bits used for CP 15
;
CONTROL_MMU EQU 0x00000001
;
; Defs used for the copying of Code into RAM
;
PHYBASE EQU 0xA7000000 ; not clear why we need this offset..
; //////////////////////////////////////////////////////////////////////
; ////////////////////// ~~~~ MACROS ~~~~ //////////////////////////////
; //////////////////////////////////////////////////////////////////////
; This macro pauses til the ost counter has advanced the specified
; number of microseconds. **Note: need to modify this to take rollovers
; into account.
MACRO
pauseMicroSecs $usec, $w1, $w2, $w3
ldr $w1, =OSCR_BASE_PHYSICAL
mov $w2, #0x4 ; 3.6864 ticks-per-usec
mov $w3, $usec
mul $w2, $w3, $w2 ; number of ticks in the desired interval
ldr $w3, [$w1] ; get start tick count
add $w3, $w3, $w2 ; compute target tick count
66
ldr $w2, [$w1] ; get current tick count
cmp $w3, $w2 ; test target against current
bhi %BT66 ; reached target?
MEND
; //////////////////////////////////////////////////////////////////////
; //////////////////////////////////////////////////////////////////////
;
; ** LUBBOCK-SPECIFIC **
;
; HwConfig is a virtual register (PWR_MAN.SPSR) in which information about the
; hardware configuration, some of it user-supplied, is stored.
; The PLL bit and the reset cause bits are loaded elsewhere, see
; the macros getResetCause and getPLL.
; If $w1 is loaded with anything but 0, then we branch around the
; detection code contained here and just load the value found in
; $w1 into the HwConfig register.
;
MACRO
setHWConfig $w1, $w2, $w3, $w4, $w5, $w6, $w7, $w8
; see if we do a simple load, or a config detection
cmp $w1, #0
movne $w8, $w1
bne PostDetection
;IF PLAT_LUBBOCK = "1"
; clear a reg to accumulate bits in
mov $w8, #0
; get the processor id info
and $w1, $w1, #0xF ; extract the stepping bits
orr $w8, $w8, $w1, LSL #8 ; insert stepping info
; see if SA1111 attached
mov $w2, #PLATREGS_PHYSICAL_BASE
ldrh $w1, [$w2, #PLAT_WHOAMI]
mov $w2, #CDC_ID_SA1111
ands $w2, $w1, $w2
orreq $w8, $w8, #HwConfig_SA1111 ; 1=sa1111 present
bicne $w8, $w8, #HwConfig_SA1111 ; 0=sa1111 not present
; see if graphics card attached
mov $w2, #VDC_ID_NONE
ands $w2, $w1, $w2
orreq $w8, $w8, #HwConfig_GRFX ; 1=video card present
bicne $w8, $w8, #HwConfig_GRFX ; 0=video card not present
; see if an expansion card is installed
mov $w2, #XDC_ID_NONE
ands $w2, $w1, $w2
orreq $w8, $w8, #HwConfig_EXPN ; 1=expansion card present
bicne $w8, $w8, #HwConfig_EXPN ; 0=expansion card not present
; determine the rom/flash type
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