readme.txt

This directory contains a code example that demonstrates the functionality of the general purpose t

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ADSP-BF561 EZ-KIT General Purpose Timer Example

Analog Devices, Inc.
DSP Division
Three Technology Way
Norwood, MA 02062

Date Created:	10/28/03

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This directory contains a code example that demonstrates the functionality
of the general purpose timers on the ADSP-BF561 EZ-KIT


Files contained in this directory:

timer.dpg						project group file
timer.dpj						VisualDSP++ project file
template.ldf            		Linker Description File
set_PLL.c               		Initializes PLL Registers
Init_SDRAM.c            		Initializes SDRAM if needed
dummy.asm               		Dummy Source file for master project
system.h                		Initializes system constants
readme.txt						This readme file

\Core A\CoreA.dpj				VisualDSP++ project file
\Core A\main.c					Main timer routine   		<------ EXAMPLE-SPECIFIC CODE
\Core A\Interrupt_Init.c		Initializes Interrupts
\Core A\Interrupt_Service.c		Sets up ISRs
\Core A\PPI0_Init.c				Sets up PPI registers
\Core A\main.h					Stores function prototypes

\Core B\CoreB.dpj				VisualDSP++ project file
\Core B\main.c					Core B idle routine
\Core B\Interrupt_Init.c		Initializes Interrupts
\Core B\Interrupt_Service.c		Sets up ISRs
\Core B\PPI1_Init.c				Sets up PPI registers
\Core B\main.h					Stores function prototypes

\Shared Memory L2\L2_SRAM.dpj	VisualDSP++ project file
\Shared Memory L2\L2_SRAM.c		L2 SRAM idle routine
\Shared Memory L2\L2_SRAM.h		L2 SRAM header file

\Shared Memory L3\L3_SDRAM.dpj	VisualDSP++ project file
\Shared Memory L3\L3_SDRAM.c	L3 SDRAM idle routine
\Shared Memory L3\L3_SDRAM.h	L3 SDRAM header file







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CONTENTS

I.	FUNCTIONAL DESCRIPTION
II.	OPERATION DESCRIPTION


I.    FUNCTIONAL DESCRIPTION

	Sets up two general purpose timers, one as a PWM output, the other as a pulse width capture input. The output timer's
	waveform is looped back to the input timer which measures the period and pulse width of the waveform. An interrupt is
	generated each time a period completes and an ISR increments a period counter. Execution is automatically halted after
	25 periods have been counted.
						

II.	  OPERATION DESCRIPTION

	- follow the "hardware setup" instructions in the main comment header in "main.c"
	- Open the project group "timer.dpg" in the VisualDSP Integrated Development Environment (IDDE):    
	- Right click on "timer" in the project window and select "Build Project" (program is then
	  loaded automatically into the processor).
	- Select "Run" from the "Debug" tab on the menu bar of VisualDSP. Execution automatically halts
	  once 25 timer periods are counted in. 
	- To view the states of the timer registers and period counter during execution, hit the stop button to 
	  halt the processor.
	- To view the timer waveform, attach an oscilloscope probe to pin 57 or 58 on the EZ-KIT's 
	  J7 Expansion Interface.