📄 xi.asm
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;数字电话程序，录音（不加密），录音（加密），放（解密）
; .version 548
.mmregs
STACK .usect "STACK",100h
;常量;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
K_BUF_SIZE .set 400 ;循环次数
STEP .set 6Ah
;TMP .set 6Ah
D_LEVEL .set 0280h
.bss state,1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.def _bsp0init
.def _dmainit
.def _bspstop
.def _firloop
.ref _sintable
.ref _dmtx
.ref _main
.def _c_int00
;串口0的初始化数据;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
K_SPCR10 .set 0000000010000001b ;串口0的初始化数据
K_SPCR20 .set 0000001011100001b
K_RCR10 .set 0000000000000000b
K_RCR20 .set 0000000000000000b
K_XCR10 .set 0000000001000000b
K_XCR20 .set 0000000001000001b
K_SRGR10 .set 0000000000010011b ;
K_SRGR20 .set 0011000000011111b
; ;
K_PCR0 .set 0000101000000000b
SPSA0 .set 38h
McBSP0 .set 39h
DXR10 .set 23h
DXR20 .set 22h
DRR10 .set 21h
DRR20 .set 20h
SWCR .set 2BH
SPCR10 .set 00h
SPCR20 .set 01h
RCR10 .set 02h
RCR20 .set 03h
XCR10 .set 04h
XCR20 .set 05h
SRGR10 .set 06h
SRGR20 .set 07h
MCR10 .set 08h
MCR20 .set 09h
RCERA0 .set 0ah
RCERB0 .set 0bh
XCERA0 .set 0ch
XCERB0 .set 0dh
PCR0 .set 0Eh
;串口0的初始化数据;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;DMA 的初始化数据;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DMPREC .set 0054h ;Channel Priority and Enable Control Register
DMSA .set 0055h ;Sub-bank Address Register
DMSDI .set 0056h ;Sub-bank Data Register with autoincrement
DMSDN .set 0057h ;Sub-bank Data Register without modification
DMSRC0 .set 00h ;Channel 0 Source Address Register
DMDST0 .set 01h ;Channel 0 Destination Address Register
DMCTR0 .set 02h ;Channel 0 Element Count Register
DMSFC0 .set 03h ;Channel 0 Sync Select and Frame Count Register
DMMCR0 .set 04h ;Channel 0 Transfer Mode Control Register
DMSRC1 .set 05h ;Channel 1 Source Address Register
DMDST1 .set 06h ;Channel 1 Destination Address Register
DMCTR1 .set 07h ;Channel 1 Element Count Register
DMSFC1 .set 08h ;Channel 1 Sync Select and Frame Count Register
DMMCR1 .set 09h ;Channel 1 Transfer Mode Control Register
DMSRC2 .set 0Ah ;Channel 2 Source Address Register
DMDST2 .set 0Bh ;Channel 2 Destination Address Register
DMCTR2 .set 0Ch ;Channel 2 Element Count Register
DMSFC2 .set 0Dh ;Channel 2 Sync Select and Frame Count Register
DMMCR2 .set 0Eh ;Channel 2 Transfer Mode Control Register
DMSRC3 .set 0Fh ;Channel 3 Source Address Register
DMDST3 .set 10h ;Channel 3 Destination Address Register
DMCTR3 .set 11h ;Channel 3 Element Count Register
DMSFC3 .set 12h ;Channel 3 Sync Select and Frame Count Register
DMMCR3 .set 13h ;Channel 3 Transfer Mode Control Register
DMSRC4 .set 14h ;Channel 4 Source Address Register
DMDST4 .set 15h ;Channel 4 Destination Address Register
DMCTR4 .set 16h ;Channel 4 Element Count Register
DMSFC4 .set 17h ;Channel 4 Sync Select and Frame Count Register
DMMCR4 .set 18h ;Channel 4 Transfer Mode Control Register
DMSRC5 .set 19h ;Channel 5 Source Address Register
DMDST5 .set 1Ah ;Channel 5 Destination Address Register
DMCTR5 .set 1Bh ;Channel 5 Element Count Register
DMSFC5 .set 1Ch ;Channel 5 Sync Select and Frame Count Register
DMMCR5 .set 1Dh ;Channel 5 Transfer Mode Control Register
DMSRCP .set 1Eh ;Source Program Page Address
DMDSTP .set 1Fh ;Destination Program Page Address
DMIDX0 .set 20h ;Element Address Index Register 0
DMIDX1 .set 21h ;Element Address Index Register 1
DMFRI0 .set 22h ;Frame Address Index Register 0
DMFRI1 .set 23h ;Frame Address Index Register 1
DMGSA .set 24h ;Global Source Address Reload Register
DMGDA .set 25h ;Global Destination Address Reload Register
DMGCR .set 26h ;Global Element Count Reload Register
DMGFR .set 27h ;Global Frame Count Reload Register
;DMA 的初始化数据;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.sect ".iptr"
_c_int00
b START
nop
nop
NMI rete
nop
nop
nop
SINT17 .space 4*16
SINT18 .space 4*16
SINT19 .space 4*16
SINT20 .space 4*16
SINT21 .space 4*16
SINT22 .space 4*16
SINT23 .space 4*16
SINT24 .space 4*16
SINT25 .space 4*16
SINT26 .space 4*16
SINT27 .space 4*16
SINT28 .space 4*16
SINT29 .space 4*16
SINT30 .space 4*16
INT0 rsbx intm
rete
nop
nop
INT1 rsbx intm
rete
nop
nop
INT2 rsbx intm
rete
nop
nop
TINT: RETE
nop
nop
nop
RINT0: rsbx intm
rete
nop
nop
XINT0: rsbx intm
rete
nop
nop
SINT6 .space 4*16
SINT7 .space 4*16
INT3: rete
nop
nop
nop
HPINT: rete
nop
nop
nop
RINT1: rete
nop
nop
nop
XINT1: RETE
nop
nop
nop
DMINT4:
RETE
nop
nop
nop
DMINT5:
BD _dmtx
nop
nop
;*************************
.text
START:
STM #STACK+100h,SP
STM #7000h,SWWSR
STM #1020h,PMST
SSBX CPL
SSBX INTM ;DINT
RSBX OVM
NOP
NOP
B _main
;*********************************************************
_firloop:
STLM A,AR6 ;把TxBuf的地址
PORTR #20h,*(state)
; ST #400h,*(state)
STM #K_BUF_SIZE,BRC
STM #1,AR0
BITF *(state),#0100h
BC NEXT1,NTC
STM _sintable,AR5
B NEXT6
NEXT1 BITF *(state),#0200h
BC NEXT2,NTC
STM _sintable+400,AR5
B NEXT6
NEXT2 BITF *(state),#0400h
BC NEXT3,NTC
STM _sintable+800,AR5
B NEXT6
NEXT3 BITF *(state),#0800h
BC NEXT4,NTC
STM _sintable+1200,AR5
B NEXT6
NEXT4 BITF *(state),#1000h
BC NEXT5,NTC
STM _sintable+1600,AR5
B NEXT6
NEXT5 BITF *(state),#2000h
BC NEXT6,NTC
STM _sintable+2000,AR5
NEXT6 RPTB LOOP-1
; STM _sintable,AR5
LD *AR5+0,A
SFTA A,-5
ADD #D_LEVEL,A
STL A,*AR6+
LOOP
RET
;*************************
;******************************
_bsp0init:
STM #SPCR10,SPSA0 ;串口0和PCM编解码器的初始化程序
STM #0000h,McBSP0 ;RESET R
NOP
NOP
STM #SPCR20,SPSA0
STM #0000h,McBSP0 ;RESET X
NOP
NOP
STM #RCR10,SPSA0
STM #K_RCR10,McBSP0
NOP
NOP
STM #XCR10,SPSA0
STM #K_XCR10,McBSP0
NOP
NOP
STM #PCR0,SPSA0
STM #K_PCR0,McBSP0
NOP
NOP
STM SRGR10,SPSA0
STM #K_SRGR10,McBSP0
NOP
NOP
STM SRGR20,SPSA0
STM #K_SRGR20,McBSP0
NOP
NOP
STM #RCR20,SPSA0
STM #K_RCR20,McBSP0
NOP
NOP
STM #XCR20,SPSA0
STM #K_XCR20,McBSP0
NOP
NOP
STM #SPCR10,SPSA0
STM #K_SPCR10,McBSP0 ;ENBLE R
NOP
NOP
STM #SPCR20,SPSA0
STM #K_SPCR20,McBSP0 ;ENBLE X
NOP
NOP
RET
;******************************
_bspstop:
STM #SPCR10,SPSA0 ;串口0和PCM编解码器的初始化程序
STM #0000h,McBSP0 ;RESET R
NOP
NOP
STM #SPCR20,SPSA0
STM #0000h,McBSP0 ;RESET X
NOP
RET
;**************************
_dmainit:
STM DMSRC5,DMSA ;set source address to DRR10
STM #3000h,DMSDI
STM DXR10,DMSDI
STM #320h ,DMSDI
STM #0010000000000000b ,DMSDI
;0010~~~~~~~~~~~~ (DSYN) McBSP0 transmit sync event
;~~~~0~~~~~~~~~~~ (DBLW) Single-word mode
;~~~~~000~~~~~~~~ Reserved
;~~~~~~~~00000000 (Frame Count) Frame count is not
; relevant in ABU mode
STM #0111000101000001b ,DMSDN
;0~~~~~~~~~~~~~~~ (AUTOINIT) Autoinitialization disabled
;~1~~~~~~~~~~~~~~ (DINM) DMA Interrupts enabled
;~~1~~~~~~~~~~~~~ (IMOD) Interrupt at half-full buffer
;~~~1~~~~~~~~~~~~ (CTMOD) ABU (non-decrement) mode
;~~~~0~~~~~~~~~~~ Reserved
;~~~~~011~~~~~~~~ (SIND) Post increment source address (DRR10)
;~~~~~~~~01~~~~~~ (DMS) Source in data space
;~~~~~~~~~~0~~~~~ Reserved
;~~~~~~~~~~~000~~ (DIND) No modify on destination address
; with DMIDX0
;~~~~~~~~~~~~~~01 (DMD) Destination in data space
STM DMIDX0,DMSA ;set element address index to +1
STM #0001h,DMSDN
STM #0011000000110000b ,DMPREC
;0~~~~~~~~~~~~~~~ (FREE) DMA stops on emulation stop
;~0~~~~~~~~~~~~~~ Reserved
;~~1~~~~~~~~~~~~~ (DPRC[5]) Channel 5 high priority
;~~~1~~~~~~~~~~~~ (DPRC[4]) Channel 4 high priority
;~~~~0~~~~~~~~~~~ (DPRC[3]) Channel 3 low priority
;~~~~~0~~~~~~~~~~ (DPRC[2]) Channel 2 low priority
;~~~~~~0~~~~~~~~~ (DPRC[1]) Channel 1 low priority
;~~~~~~~0~~~~~~~~ (DPRC[0]) Channel 0 low priority
;~~~~~~~~00~~~~~~ (INTOSEL) N/A
;~~~~~~~~~~1~~~~~ (DE[5]) Channel 5 enabled
;~~~~~~~~~~~1~~~~ (DE[4]) Channel 4 enabled
;~~~~~~~~~~~~0~~~ (DE[3]) Channel 3 disabled
;~~~~~~~~~~~~~0~~ (DE[2]) Channel 2 disabled
;~~~~~~~~~~~~~~0~ (DE[1]) Channel 1 disabled
;~~~~~~~~~~~~~~~0 (DE[0]) Channel 0 disabled
RET
;*************************
.end
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