📄 net_nic.c
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MAC1 = MAC1_RESET_TX | /* [15],[14],[11:8] -> soft resets all MAC internal modules */
MAC1_RESET_MCS_TX |
MAC1_RESET_RX |
MAC1_RESET_MCS_RX |
MAC1_RESET_SIM |
MAC1_RESET_SOFT;
COMMAND = COMMAND_RESET_REG | /* Reset all datapaths and host registers */
COMMAND_RESET_TX |
COMMAND_RESET_RX;
NetBSP_DlyMs(2); /* Delay for a few milliseconds after reset */
MAC1 = 0; /* Deassert all prior resets */
EMAC_TxDis(); /* Disable the transmitter */
EMAC_RxDis(); /* Disable the receiver */
#if EMAC_CFG_RMII
COMMAND |= COMMAND_RMII; /* Configure EMAC / PHY communication to RMII mode */
#else
COMMAND &= ~COMMAND_RMII; /* Configure EMAC / PHY communication to MII mode */
#endif
SUPP = 0x0000; /* Assume and configure RMII link speed logic for 10Mbit */
NetBSP_DlyMs(2); /* Delay for a few milliseconds after reset */
TEST = 0; /* Default the test register. No tests in progress */
MAXF = 0x600; /* Accept maximum sized frames, 1536 octects (default) */
MAC1 |= MAC1_PASS_ALL_FRAMES; /* Pass All Frames: Normal and Control */
MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; /* Configure the EMAC to PAD short frames and append CRC */
RXFILTERCTRL = ACCEPT_BROADCAST | ACCEPT_PERFECT; /* Accept Broadcast and Perfect Address frames */
/* ---- Configure the MDI port (RMII / MII capable) ------- */
clk_freq = NetBSP_GetHostClkFreq(); /* Get the LPC23xx/LPC24xx cClkFrq (Hz) which feeds the EMAC*/
clk_freq /= 100000; /* Div by 1000000 for MHz, Mult by 10 so floating point */
/* math not necessary when calculating the divider below */
MCFG |= 0x8018; /* Apply a reset to the MII logic, set default divider = 20 */
MCMD = 0; /* Clear MII command register */
for (i = 0; i < 7; i++) { /* Check dividers to yield MII frequency ~2.5 MHz */
if ((clk_freq / MII_Dividers[i][0]) <= 25) { /* Index [i][0] = decimal div value, [i][1] = MCFG reg val */
MCFG = MII_Dividers[i][1]; /* Remove reset, set proper MIIM divider */
break;
}
}
NetBSP_DlyMs(10); /* Short delay while PHY exits reset and new divider is set */
NetNIC_PhyInit(perr); /* --------------- Initialize the PHY --------------------- */
IPGR = 0x0C12; /* Set the Non Back to Back Inter Pkt Gap to recm'd value */
CLRT = 0x370F; /* Collission Windows Retry register (default value) */
SA0 = (NetIF_MAC_Addr[5] << 8) | /* Write the MAC Address, octect 2 and 1 to the EMAC */
(NetIF_MAC_Addr[4]);
SA1 = (NetIF_MAC_Addr[3] << 8) | /* Write the MAC Address, octect 4 and 3 to the EMAC */
(NetIF_MAC_Addr[2]);
SA2 = (NetIF_MAC_Addr[1] << 8) | /* Write the MAC Address, octect 6 and 5 to the EMAC */
(NetIF_MAC_Addr[0]);
NetIF_MAC_AddrValid = DEF_YES; /* Inform uC/TCP-IP, that we have a valid MAC address set */
/* ----- Descriptor List Global Pointer Initialization ---- */
RxDesc = (EMAC_DESCRIPTOR *)(EMAC_RX_DESC_BASE_ADDR);
TxDesc = (EMAC_DESCRIPTOR *)(EMAC_TX_DESC_BASE_ADDR);
RxStatus = (RX_STATUS *)(EMAC_RX_STATUS_BASE_ADDR);
TxStatus = (TX_STATUS *)(EMAC_TX_STATUS_BASE_ADDR);
RxBufBaseAddr = (CPU_INT08U *)(EMAC_RX_BUFF_BASE_ADDR);
TxBufBaseAddr = (CPU_INT08U *)(EMAC_TX_BUFF_BASE_ADDR);
/* ---------------- Rx Descriptor Initialization ----------- */
/* Rx Descriptor and Status array initialization */
/* Set the addr of the DMA Rx buf */
/* Interrupt when Rx complete, set buf size (-1 encoded) */
/* Initialize the Status Info to 0 */
/* Initialize the Status Hash CRC to 0 */
for (i = 0; i < EMAC_NUM_RX_DESC; i++) {
RxDesc[i].PacketAddr = (CPU_INT32U)(RxBufBaseAddr + (i * EMAC_RX_BUF_SIZE));
RxDesc[i].Control = EMAC_RX_DESC_INT | (EMAC_RX_BUF_SIZE - 1);
RxStatus[i].StatusInfo = 0;
RxStatus[i].StatusHashCRC = 0;
}
RXDESCRIPTOR = (CPU_INT32U)(RxDesc); /* Write the Rx Descriptor base address register */
RXSTATUS = (CPU_INT32U)(RxStatus); /* Write the Rx Status base address register */
RXDESCRIPTORNUMBER = EMAC_NUM_RX_DESC - 1; /* Write the Rx Descriptor Number register with NumDesc - 1 */
RXCONSUMEINDEX = 0; /* Configure the Rx Consume Index register to 0 */
/* ------- Tx Descriptor and Status Initialization -------- */
/* Rx Descriptor and Status array initialization */
/* Set the addr of the DMA Rx buf, assume 1536B frames */
/* Configure the control bits in the EMAC_TxPkt() function */
/* Initialize the Status Info to 0 */
for (i = 0; i < EMAC_NUM_TX_DESC; i++) {
TxDesc[i].PacketAddr = (CPU_INT32U)(TxBufBaseAddr + (i * 1536));
TxDesc[i].Control = 0;
TxStatus[i].StatusInfo = 0;
}
TXDESCRIPTOR = (CPU_INT32U)(TxDesc); /* Write the Tx Descriptor base address register */
TXSTATUS = (CPU_INT32U)(TxStatus); /* Write the Tx Status base address register */
TXDESCRIPTORNUMBER = EMAC_NUM_TX_DESC - 1; /* Write the Tx Descriptor Number register with NumDesc - 1 */
TXPRODUCEINDEX = 0; /* Configure the Tx Produce Index register to 0 */
/* ------- Configure Interrupts on the VIC Level ---------- */
INTCLEAR = (INT_RX_OVERRUN | /* Clear all EMAC interrupt sources */
INT_RX_ERROR |
INT_RX_FINISHED |
INT_RX_DONE |
INT_TX_UNDERRUN |
INT_TX_ERROR |
INT_TX_FINISHED |
INT_TX_DONE |
INT_SOFT |
INT_WAKEUP);
NetNIC_IntInit();
/* -------- Enable the transmitter and receiver ----------- */
EMAC_TxEn(); /* Enable the EMAC transmitter */
EMAC_RxEn(); /* Enable the EMAC receiver */
*perr = NET_NIC_ERR_NONE; /* Initialize the returned error code to NO Error */
}
/*
*********************************************************************************************************
* NIC_RxGetNRdy()
*
* Description : Determines how many packets we are ready to be processed.
*
* Parameters : None.
*
* Returns : Number of NIC buffers that are ready to be processed by the stack.
*********************************************************************************************************
*/
static CPU_INT16U NIC_RxGetNRdy (void)
{
CPU_INT16U n_rdy;
CPU_INT16U rxconsumeix;
CPU_INT16U rxproduceix;
rxconsumeix = RXCONSUMEINDEX;
rxproduceix = RXPRODUCEINDEX;
if (rxproduceix < rxconsumeix) { /* If the produce index has wrapped around */
n_rdy = EMAC_NUM_RX_DESC - rxconsumeix + rxproduceix;
} else { /* If consumeix is < produceix, then no wrap around occured */
n_rdy = rxproduceix - rxconsumeix;
}
return (n_rdy);
}
/*
*********************************************************************************************************
*********************************************************************************************************
* LOCAL FUNCTIONS: EMAC RX FUNCTIONS
*********************************************************************************************************
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* EMAC_RxEn()
*
* Description : Enable LPC23XX/LPC24XX EMAC Receiver.
*
* Argument(s) : none.
*
* Return(s) : none.
*
* Caller(s) : EMAC_Init().
*********************************************************************************************************
*/
static void EMAC_RxEn (void)
{
COMMAND |= COMMAND_RX_EN; /* Enable the receiver */
MAC1 |= COMMAND_RX_EN; /* Enable the receiver */
}
/*
*********************************************************************************************************
* EMAC_RxDis()
*
* Description : Disable LPC23XX/LPC24XX EMAC Receiver.
*
* Argument(s) : none.
*
* Return(s) : none.
*
* Caller(s) : EMAC_Init().
*********************************************************************************************************
*/
static void EMAC_RxDis (void)
{
COMMAND &= ~COMMAND_RX_EN; /* Disable the receiver */
MAC1 &= ~COMMAND_RX_EN; /* Disable the receiver (same bit position as COMMAND reg) */
}
/*
*********************************************************************************************************
* EMAC_RxIntEn()
*
* Description : Enable EMAC Receiver Interrupts.
*
* Argument(s) : none.
*
* Return(s) : none.
*
* Caller(s) : NetNIC_IntEn(), NetNIC_RxPktGetSize(), NetNIC_RxPkt().
*
* Notes : 1) The RxDone interrupt occurs when a Rx descriptor has been produced by the EMAC.
*********************************************************************************************************
*/
static void EMAC_RxIntEn (void)
{
INTENABLE |= (INT_RX_DONE | INT_RX_OVERRUN); /* Enable RxDone interrupts and Rx Overrun interrupts */
}
/*
*********************************************************************************************************
* EMAC_RxPkt()
*
* D⌨️ 快捷键说明
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