📄 net_nic.c
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/*
*********************************************************************************************************
* uC/TCP-IP
* The Embedded TCP/IP Suite
*
* (c) Copyright 2003-2007; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
*
* uC/TCP-IP is provided in source form for FREE evaluation, for educational
* use or peaceful research. If you plan on using uC/TCP-IP in a commercial
* product you need to contact Micrium to properly license its use in your
* product. We provide ALL the source code for your convenience and to help
* you experience uC/TCP-IP. The fact that the source code is provided does
* NOT mean that you can use it without paying a licensing fee.
*
* Network Interface Card (NIC) port files provided, as is, for FREE and do
* NOT require any additional licensing or licensing fee.
*
* Knowledge of the source code may NOT be used to develop a similar product.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* NETWORK INTERFACE CARD
*
* LPC23XX/LPC24XX EMAC
*
* Filename : net_nic.c
* Version : V1.90
* Programmer(s) : EHS
*********************************************************************************************************
* Note(s) : (1) Supports EMAC section of NXP's LPC23XX and LPC24XX microcontrollers
* as described in
*
* NXP Corporation (NXP; http://www.nxp.com).
* (a) "LPC2364/6/8/78 User Manual" (UM10211) Revision 01 ( 6 October 2006)
* (b) "LPC2468 User Manual" (UM10237) Revision 01 (18 December 2006)
*
* (2) REQUIREs Ethernet Network Interface Layer located in the following network directory :
*
* \<Network Protocol Suite>\IF\Ether\
*
* where
* <Network Protocol Suite> directory path for network protocol suite.
*
* (2) Since the EMAC module is integrated into either an LPC23XX or LPC24XX microcontroller,
* the endianness of the registers is the same as the CPU, which is little-endian by
* default.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* INCLUDE FILES
*********************************************************************************************************
*/
#define NET_NIC_MODULE
#include <net.h>
#include <net_phy.h>
#include <net_phy_def.h>
/*
*********************************************************************************************************
* NXP LPC23xx/LPC24xx REGISTERS
*********************************************************************************************************
*/
#define PCONP (*((volatile CPU_INT32U *)0xE01FC0C4))
/*
*********************************************************************************************************
* NXP LPC23xx/LPC24xx EMAC REGISTERS
*
* Note(s) : (1) See NXP LPC23XX or NXP LPC24XX documentation for register summary.
*
* (2) Since the EMAC module is integrated into either a LPC23XX or LPC24XX microcontroller,
* the endianness of the registers is the same as the CPU, which is little-endian by default.
*********************************************************************************************************
*/
/* ------------- MAC REGISTERS ---------------- */
#define MAC1 (*((volatile CPU_INT32U *)0xFFE00000)) /* MAC Configuration Register 1 */
#define MAC2 (*((volatile CPU_INT32U *)0xFFE00004)) /* MAC Configuration Register 2 */
#define IPGT (*((volatile CPU_INT32U *)0xFFE00008)) /* Back-to-Back Inter-Packet-Gap Register */
#define IPGR (*((volatile CPU_INT32U *)0xFFE0000C)) /* Non Back-to-Back Inter-Packet-Gap Register */
#define CLRT (*((volatile CPU_INT32U *)0xFFE00010)) /* Collision Window/Retyr Register */
#define MAXF (*((volatile CPU_INT32U *)0xFFE00014)) /* Maximum Frame Register */
#define SUPP (*((volatile CPU_INT32U *)0xFFE00018)) /* PHY Support Register */
#define TEST (*((volatile CPU_INT32U *)0xFFE0001C)) /* Test Register */
#define MCFG (*((volatile CPU_INT32U *)0xFFE00020)) /* MII Mgmt Configuration Register */
#define MCMD (*((volatile CPU_INT32U *)0xFFE00024)) /* MII Mgmt Command Register */
#define MADR (*((volatile CPU_INT32U *)0xFFE00028)) /* MII Mgmt Address Register */
#define MWTD (*((volatile CPU_INT32U *)0xFFE0002C)) /* MII Mgmt Write Data Register */
#define MRDD (*((volatile CPU_INT32U *)0xFFE00030)) /* MII Mgmt Read Data Register */
#define MIND (*((volatile CPU_INT32U *)0xFFE00034)) /* MII Mgmt Indicators Register */
#define SA0 (*((volatile CPU_INT32U *)0xFFE00040)) /* Station Address 0 Register */
#define SA1 (*((volatile CPU_INT32U *)0xFFE00044)) /* Station Address 1 Register */
#define SA2 (*((volatile CPU_INT32U *)0xFFE00048)) /* Station Address 2 Register */
/* ----------- CONTROL REGISTERS -------------- */
#define COMMAND (*((volatile CPU_INT32U *)0xFFE00100)) /* Command Register */
#define STATUS (*((volatile CPU_INT32U *)0xFFE00104)) /* Status Register */
#define RXDESCRIPTOR (*((volatile CPU_INT32U *)0xFFE00108)) /* Receive Descriptor Base Address Register */
#define RXSTATUS (*((volatile CPU_INT32U *)0xFFE0010C)) /* Receive Status Base Address Register */
#define RXDESCRIPTORNUMBER (*((volatile CPU_INT32U *)0xFFE00110)) /* Receive Number of Descriptors Register */
#define RXPRODUCEINDEX (*((volatile CPU_INT32U *)0xFFE00114)) /* Receive Produce Index Register */
#define RXCONSUMEINDEX (*((volatile CPU_INT32U *)0xFFE00118)) /* Receive Consume Index Register */
#define TXDESCRIPTOR (*((volatile CPU_INT32U *)0xFFE0011C)) /* Transmit Descriptor Base Address Register */
#define TXSTATUS (*((volatile CPU_INT32U *)0xFFE00120)) /* Transmit Status Base Address Register */
#define TXDESCRIPTORNUMBER (*((volatile CPU_INT32U *)0xFFE00124)) /* Transmit Number of Descriptors Register */
#define TXPRODUCEINDEX (*((volatile CPU_INT32U *)0xFFE00128)) /* Transmit Produce Index Register */
#define TXCONSUMEINDEX (*((volatile CPU_INT32U *)0xFFE0012C)) /* Transmit Consume Index Register */
#define TSV0 (*((volatile CPU_INT32U *)0xFFE00158)) /* Transmit Status Vector 0 Register */
#define TSV1 (*((volatile CPU_INT32U *)0xFFE0015C)) /* Transmit Status Vector 1 Register */
#define RSV (*((volatile CPU_INT32U *)0xFFE00160)) /* Receive Status Vector Register */
#define FLOWCONTROLCOUNTER (*((volatile CPU_INT32U *)0xFFE00170)) /* Flow Control Counter Register */
#define FLOWCONTROLSTATUS (*((volatile CPU_INT32U *)0xFFE00174)) /* Flow Control Status Register */
/* ---------- RX FILTER REGISTERS ------------- */
#define RXFILTERCTRL (*((volatile CPU_INT32U *)0xFFE00200)) /* Receive Filter Control Register */
#define RXFILTERWOLSTATUS (*((volatile CPU_INT32U *)0xFFE00204)) /* Receive Filter WoL Status Register */
#define RXFILTERWOLCLEAR (*((volatile CPU_INT32U *)0xFFE00208)) /* Receive Filter WoL Clear Register */
#define HASHFILTERL (*((volatile CPU_INT32U *)0xFFE00210)) /* Hash Filter Table LSBs Register */
#define HASHFILTERH (*((volatile CPU_INT32U *)0xFFE00214)) /* Hash Filter Table MSBs Register */
/* -------- MODULE CONTROL REGISTERS ---------- */
#define INTSTATUS (*((volatile CPU_INT32U *)0xFFE00FE0)) /* Interrupt status register */
#define INTENABLE (*((volatile CPU_INT32U *)0xFFE00FE4)) /* Interrupt enable register */
#define INTCLEAR (*((volatile CPU_INT32U *)0xFFE00FE8)) /* Interrupt clear register */
#define INTSET (*((volatile CPU_INT32U *)0xFFE00FEC)) /* Interrupt set register */
#define POWERDOWN (*((volatile CPU_INT32U *)0xFFE00FF4)) /* Power-down register */
/*
*********************************************************************************************************
* NXP LPC23xx/LPC24xx EMAC REGISTER BITS
*********************************************************************************************************
*/
/* ----------------- MAC1 bits ---------------- */
#define MAC1_RX_ENABLE DEF_BIT_00
#define MAC1_PASS_ALL_FRAMES DEF_BIT_01
#define MAC1_RESET_TX DEF_BIT_08
#define MAC1_RESET_MCS_TX DEF_BIT_09
#define MAC1_RESET_RX DEF_BIT_10
#define MAC1_RESET_MCS_RX DEF_BIT_11
#define MAC1_RESET_SIM DEF_BIT_14
#define MAC1_RESET_SOFT DEF_BIT_15
/* ----------------- MAC2 bits ---------------- */
#define MAC2_FULL_DUPLEX DEF_BIT_00
#define MAC2_CRC_EN DEF_BIT_08
#define MAC2_PAD_EN DEF_BIT_09
/* ----------------- IPGT bits ---------------- */
#define IPG_HALF_DUP 0x0012
#define IPG_FULL_DUP 0x0015
/* ----------------- SUPP bits ---------------- */
#define SUPP_SPEED DEF_BIT_08
/* ----------------- MCFG bits ---------------- */
#define MCFG_CLKSEL_DIV4 0x0000
#define MCFG_CLKSEL_DIV6 0x0008
#define MCFG_CLKSEL_DIV8 0x000C
#define MCFG_CLKSEL_DIV10 0x0010
#define MCFG_CLKSEL_DIV14 0x0014
#define MCFG_CLKSEL_DIV20 0x0018
#define MCFG_CLKSEL_DIV28 0x001C
#define MCFG_RESET_MII_MGMT DEF_BIT_15
/* ----------------- MCMD bits ---------------- */
#define MCMD_WRITE DEF_BIT_NONE
#define MCMD_READ DEF_BIT_00
/* --------------- COMMAND bits --------------- */
#define COMMAND_RX_EN DEF_BIT_00
#define COMMAND_TX_EN DEF_BIT_01
#define COMMAND_RESET_REG DEF_BIT_03
#define COMMAND_RESET_TX DEF_BIT_04
#define COMMAND_RESET_RX DEF_BIT_05
#define COMMAND_PASS_RUNT_FRAMES DEF_BIT_06
#define COMMAND_PASS_ALL_FRAMES DEF_BIT_07
#define COMMAND_RMII DEF_BIT_09
#define COMMAND_FULL_DUPLEX DEF_BIT_10
/* -------------- INTENABLE bits -------------- */
/* -------------- INTSTATUS bits -------------- */
/* -------------- INTCLEAR bits -------------- */
/* -------------- INTSET bits -------------- */
#define INT_RX_OVERRUN DEF_BIT_00
#define INT_RX_ERROR DEF_BIT_01
#define INT_RX_FINISHED DEF_BIT_02
#define INT_RX_DONE DEF_BIT_03
#define INT_TX_UNDERRUN DEF_BIT_04
#define INT_TX_ERROR DEF_BIT_05
#define INT_TX_FINISHED DEF_BIT_06
#define INT_TX_DONE DEF_BIT_07
#define INT_SOFT DEF_BIT_12
#define INT_WAKEUP DEF_BIT_13
/* ------------- RXFILTERCTRL bits ------------ */
#define ACCEPT_BROADCAST DEF_BIT_01
#define ACCEPT_PERFECT DEF_BIT_05
/*
*********************************************************************************************************
* DESCRIPTOR CONTROL AND STATUS BIT DEFINITIONS
*********************************************************************************************************
*/
#define EMAC_TX_DESC_INT 0x80000000 /* EMAC Descriptor Tx and Rx Control bits */
#define EMAC_TX_DESC_LAST 0x40000000
#define EMAC_TX_DESC_CRC 0x20000000
#define EMAC_TX_DESC_PAD 0x10000000
#define EMAC_TX_DESC_HUGE 0x08000000
#define EMAC_TX_DESC_OVERRIDE 0x04000000
#define EMAC_RX_DESC_INT 0x80000000
#define TX_DESC_STATUS_ERR 0x80000000 /* EMAC Tx Status bits */
#define TX_DESC_STATUS_NODESC 0x40000000
#define TX_DESC_STATUS_UNDERRUN 0x20000000
#define TX_DESC_STATUS_LCOL 0x10000000
#define TX_DESC_STATUS_ECOL 0x08000000
#define TX_DESC_STATUS_EDEFER 0x04000000
#define TX_DESC_STATUS_DEFER 0x02000000
#define TX_DESC_STATUS_COLCNT 0x01E00000
#define RX_DESC_STATUS_ERR 0x80000000 /* EMAC Rx Status bits */
#define RX_DESC_STATUS_LAST 0x40000000
#define RX_DESC_STATUS_NODESC 0x20000000
#define RX_DESC_STATUS_OVERRUN 0x10000000
#define RX_DESC_STATUS_ALGNERR 0x08000000
#define RX_DESC_STATUS_RNGERR 0x04000000
#define RX_DESC_STATUS_LENERR 0x02000000
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