usrdef.h
来自「基于ARM和uC/OS-II实现的串口控制台」· C头文件 代码 · 共 326 行
H
326 行
#ifndef __USRDEF_H__
#define __USRDEF_H__
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#define DWORD uint32
#define BOOL uint8
#define MAKEWORD(L, H) ((WORD)(H << 8 | L))
#define MAKEDWORD(L, H) ((DWORD)(H << 16 | L))
#define LOBYTE(x) ((BYTE)(x & 0xFF))
#define HIBYTE(x) ((BYTE)(x >> 8))
#define LOWORD(x) ((WORD)(x & 0xFFFF))
#define HIWORD(x) ((WORD)(x >> 16))
/*********** Pin Connect Block **start********/
#define FIRST 1
#define SECOND 2
#define THIRD 3
/* PINSEL0 */
#define UART0_TXD (FIRST << 0)
#define UART0_RXD (FIRST << 2)
#define I2C_SCL (FIRST << 4)
#define I2C_SDA (FIRST << 6)
#define SPI0_SCK (FIRST << 8)
#define SPI0_MISO (FIRST << 10)
#define SPI0_MOSI (FIRST << 12)
#define SPI0_SSEL (FIRST << 14)
#define UART1_TXD (FIRST << 16)
#define UART1_RXD (FIRST << 18)
#define UART1_RTS (FIRST << 20)
#define UART1_CTS (FIRST << 22)
#define UART1_DSR (FIRST << 24)
#define UART1_DTR (FIRST << 26)
#define UART1_DCD (FIRST << 28)
#define UART1_RI (FIRST << 30)
#define PWM1 (SECOND << 0)
#define PWM3 (SECOND << 2)
#define SEL0_TIMER0_CAPTURE00 (SECOND << 4)
#define SEL0_TIMER0_MATCH00 (SECOND << 6)
#define SEL0_TIMER0_CAPTURE01 (SECOND << 8)
#define SEL0_TIMER0_MATCH01 (SECOND << 10)
#define SEL0_TIMER0_CAPTURE02 (SECOND << 12)
#define PWM2 (SECOND << 14)
#define PWM4 (SECOND << 16)
#define PWM6 (SECOND << 18)
#define SEL0_TIMER1_CAPTURE10 (SECOND << 20)
#define SEL0_TIMER1_CAPTURE11 (SECOND << 22)
#define SEL0_TIMER1_MATCH10 (SECOND << 24)
#define SEL0_TIMER1_MATCH11 (SECOND << 26)
#define SEL0_1_EINT1 (SECOND << 28)
#define SEL0_1_EINT2 (SECOND << 30)
#define SEL0_EINT0 (THIRD << 2)
#define SEL0_2_EINT1 (THIRD << 6)
#define SEL0_AD06 (THIRD << 8)
#define SEL0_AD07 (THIRD << 10)
#define SEL0_AD10 (THIRD << 12)
#define SEL0_2_EINT2 (THIRD << 14)
#define SEL0_AD11 (THIRD << 16)
#define SEL0_EINT3 (THIRD << 18)
#define SEL0_AD12 (THIRD << 20)
#define SEL0_I2C1_SCL1 (THIRD << 22)
#define SEL0_AD13 (THIRD << 24)
#define SEL0_AD14 (THIRD << 26)
#define SEL0_I2C1_SDA1 (THIRD << 28)
#define SEL0_AD15 (THIRD << 30)
/* PINSEL1 */
#define SEL1_EINT0 (FIRST << 0)
#define TIMER1_CAPTURE12 (FIRST << 2)
#define TIMER1_CAPTURE13 (FIRST << 4)
#define TIMER1_MATCH12 (FIRST << 6)
#define TIMER1_MATCH13 (FIRST << 8)
#define PWM5 (FIRST << 10)
#define SEL0_AD17 (THIRD << 12)
#define SEL0_AD04 (THIRD << 18)
#define SEL0_AD05 (THIRD << 20)
#define SEL0_AD00 (FIRST << 22)
#define SEL0_AD01 (FIRST << 24)
#define SEL0_AD02 (FIRST << 26)
#define SEL0_AD03 (FIRST << 28)
#define SEL1_TINER0_MATCH02 (SECOND << 0)
#define SPI1_SCK (SECOND << 2)
#define SPI1_MISO (SECOND << 4)
#define SPI1_MOSI (SECOND << 6)
#define SPI1_SSEL (SECOND << 8)
#define SEL1_1_TIMER0_CAPTURE00 (SECOND << 12)
#define SEL1_TIMER0_CAPTURE01 (SECOND << 22)
#define SEL1_TIMER0_CAPTURE02 (SECOND << 24)
#define SEL1_TIMER0_CAPTURE03 (SECOND << 26)
#define SEL1_1_EINT3 (SECOND << 28)
#define SEL1_TIMER1_MATCH12 (THIRD << 2)
#define SEL1_1_TIMER1_MATCH13 (THIRD << 4)
#define SEL1_2_TIMER1_MATCH13 (THIRD << 6)
#define SEL1_2_EINT3 (THIRD << 8)
#define SEL1_TIMER1_CAPTURE13 (THIRD << 10)
#define SEL1_TIMER0_MATCH00 (THIRD << 12)
#define SEL1_TIMER0_MATCH01 (THIRD << 22)
#define SEL1_TIMER0_MATCH02 (THIRD << 24)
#define SEL1_TIMER0_MATCH03 (THIRD << 26)
#define SEL1_2_TIMER0_CAPTURE00 (THIRD << 28)
/*********** Pin Connect Block **end********/
/*********** UART0 **start********/
/* U0LCR */
#define U0LCR_DATA_5BITS 0x00
#define U0LCR_DATA_6BITS 0x01
#define U0LCR_DATA_7BITS 0x02
#define U0LCR_DATA_8BITS 0x03
#define U0LCR_STOP_1BIT 0x00
#define U0LCR_STOP_2BITS 0x04
#define U0LCR_DIS_PARITY 0x00
#define U0LCR_EN_PARITY 0x08
#define U0LCR_ODD 0x00
#define U0LCR_EVEN 0x10
#define U0LCR_FORCE1 0x20
#define U0LCR_FORCE0 0x30
#define U0LCR_DIS_INTERCTL 0x00
#define U0LCR_EN_INTERCTL 0x40
#define U0LCR_DIS_DIV 0x00
#define U0LCR_EN_DIV 0x80
/* U0FCR */
#define U0FCR_FIFO 0x01
#define U0FCR_RX_1_TOUCH 0x00
#define U0FCR_RX_4_TOUCH 0x40
#define U0FCR_RX_8_TOUCH 0x80
#define U0FCR_RX_14_TOUCH 0xC0
/* U0IER */
#define U0IER_RBR 0x01
#define U0IER_THRE 0x02
#define U0IER_LINES 0x04
/* U0LSR */
#define U0LSR_RDR 0x01
#define U0LSR_OE 0x02
#define U0LSR_PE 0x04
#define U0LSR_FE 0x08
#define U0LSR_BI 0x10
#define U0LSR_THRE 0x20
#define U0LSR_TEMT 0x40
#define U0LSR_RXFE 0x80
/* U0IIR */ //Priority:
#define U0IIR_LINES 0x06 //Highest
#define U0IIR_RX 0x04 //Second
#define U0IIR_TIMEOUT 0x0C //Second
#define U0IIR_THRE 0x02 //Third
/* U0TER */
#define U0TER_DIS_TXEN 0x00
#define U0TER_EN_TXEN 0x80
/*********** UART0 **end**********/
/* VICVectCntl0 ~ VICVectCntl15 */
#define EN_IRQ 0x20
/* 中断源 */
#define IRQ_WDT 0
#define IRQ_RES 1
#define IRQ_ARM_KERNEL1 2
#define IRQ_ARM_KERNEL2 3
#define IRQ_TIMER0 4
#define IRQ_TIMER1 5
#define IRQ_UART0 6
#define IRQ_UART1 7
#define IRQ_PWM0 8
#define IRQ_I2C 9
#define IRQ_SPI0 10
#define IRQ_SPI1 11
#define IRQ_PLL 12
#define IRQ_RTC 13
#define IRQ_EINT0 14
#define IRQ_EINT1 15
#define IRQ_EINT2 16
#define IRQ_EINT3 17
#define IRQ_AD 18
/* VICIntEnable */
#define EN_IRQ_WDT (1 << IRQ_WDT)
#define EN_IRQ_RES (1 << IRQ_RES)
#define EN_IRQ_ARM_KERNEL1 (1 << IRQ_ARM_KERNEL1)
#define EN_IRQ_ARM_KERNEL2 (1 << IRQ_ARM_KERNEL2)
#define EN_IRQ_TIMER0 (1 << IRQ_TIMER0)
#define EN_IRQ_TIMER1 (1 << IRQ_TIMER1)
#define EN_IRQ_UART0 (1 << IRQ_UART0)
#define EN_IRQ_UART1 (1 << IRQ_UART1)
#define EN_IRQ_PWM0 (1 << IRQ_PWM0)
#define EN_IRQ_I2C (1 << IRQ_I2C)
#define EN_IRQ_SPI0 (1 << IRQ_SPI0)
#define EN_IRQ_SPI1 (1 << IRQ_SPI1)
#define EN_IRQ_PLL (1 << IRQ_PLL)
#define EN_IRQ_RTC (1 << IRQ_RTC)
#define EN_IRQ_EINT0 (1 << IRQ_EINT0)
#define EN_IRQ_EINT1 (1 << IRQ_EINT1)
#define EN_IRQ_EINT2 (1 << IRQ_EINT2)
#define EN_IRQ_EINT3 (1 << IRQ_EINT3)
#define EN_IRQ_AD (1 << IRQ_AD)
/* Clean EXTINT */
#define CLR_IRQ_EINT0 0x01
#define CLR_IRQ_EINT1 0x02
#define CLR_IRQ_EINT2 0x04
#define CLR_IRQ_EINT3 0x08
/* T0/T1 MCR */
#define TIMER_INT_MR0 0x001
#define TIMER_RST_MR0 0x002
#define TIMER_STOP_MR0 0x004
#define TIMER_INT_MR1 0x008
#define TIMER_RST_MR1 0x010
#define TIMER_STOP_MR1 0x020
#define TIMER_INT_MR2 0x040
#define TIMER_RST_MR2 0x080
#define TIMER_STOP_MR2 0x100
#define TIMER_INT_MR3 0x200
#define TIMER_RST_MR3 0x400
#define TIMER_STOP_MR3 0x800
/* T0/T1 TCR */
#define TIMER_DISABLE 0x00
#define TIMER_EN 0x01
#define TIMER_RST 0x02
/* T0/T1 IR */
#define IR_MR0 0x01
#define IR_MR1 0x02
#define IR_MR2 0x04
#define IR_MR3 0x08
#define IR_CR0 0x10
#define IR_CR1 0x20
#define IR_CR2 0x40
#define IR_CR3 0x80
///////////////////////////////////////////
/*Yangfan*/
/* 中断源 */
#define IRQ_SOFT 1
/* 外部中断定义*/
#define INT0SET (0x01)
#define INT1SET (0x01<<1)
#define INT2SET (0x01<<2)
#define INT3SET (0x01<<3)
/* 引脚选择PINSEL0 */
#define PS0_EINT2PIN ((uint32)0x02<<30)
#define PS0_EINT2MSK ((uint32)0x03<<30)
#define PS1_P0_25RST ((uint32)0x03<<18)
/* IO 引脚定义*/
#define P0_NETRST ((uint32)0x01<<25)
#define P0_NETLINK ((uint32)0x01<<16)
#define P0_BUZZER ((uint32)0x01<<23)
#define P0_FPGADONE ((uint32)0x01<<19)
#define P0_FPGARST ((uint32)0x01<<28)
#define P1_CPLDRST ((uint32)0x01<<17)
#define P1_CPLDRDY ((uint32)0x01<<18)
#define NETSTATE (IO0PIN & P0_NETLINK)
/* PINSEL0 */
#define SEL0_14_EINT1 (SECOND << 28) //p0.14
#define SEL0_15_EINT2 (SECOND << 30) //p0.15
#define SEL0_1_EINT0 (THIRD << 2) //p0.1
#define SEL0_3_EINT1 (THIRD << 6) //p0.3
#define SEL0_7_EINT2 (THIRD << 14) //p0.7
#define SEL0_9_EINT3 (THIRD << 18) //p0.9
/* PINSEL1 */
#define SEL1_16_EINT0 (FIRST << 0) //p0.16
#define SEL1_30_EINT3 (SECOND << 28) //p0.30
#define SEL1_20_EINT3 (THIRD << 8) //p0.20
/* 设备状态*/
#define CMS_DS_DEXIST ((uint32)1<<0) /* 密码设备存在*/
#define CMS_DS_WDTRST ((uint32)1<<1) /* WatchDog 复位*/
#define CMS_DS_AUTHOK ((uint32)1<<2) /* 开机认证成功*/
#define CMS_DS_CFGOK ((uint32)1<<3) /* 规则配置已分发*/
#define CMS_DS_DEKOK ((uint32)1<<4) /* DEK 已分发*/
#define CMS_DS_XERROR ((uint32)1<<31) /* 密码机出现异常*/
extern uint8 SysStatus;
#define SYS_SELF_TEST 1 /* 自检状态 */
#define SYS_WAIT_CFG 2 /* 等待下发规则和密钥状态 */
#define SYS_COMM 3 /* 通信状态 */
#define SetSysStatus(x) SysStatus = x
#define GetSysStatus() SysStatus
extern uint8 FPGARuleCheck;
#define FPGA_RULE_CHECK 1 /* FPGA规则检测状态 */
#define FPGA_RULE_CHANGE 2 /* FPGA规则改变状态 */
#define FPGA_RULE_UPDATE 3 /* FPGA规则更新状态 */
#define FPGA_RULE_ERR 4 /* FPGA规则异常 */
#define SetFPGACheckStatus(x) FPGARuleCheck = x
#define GetFPGACheckStatus() FPGARuleCheck
#endif
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