pipectrl.v

别处下载的sarm9

/********************************************************************************/
/* Copyright @ 2006 by SOME of SJTU                                             */
/* All rights are reserved. Reproduction in whole or in part is                 */
/* prohibited without the written consent of the copyright owner.               */
/* SJTU reserves the right to make changes without notice at                    */
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/* no warranty, expressed, implied or statutory, including but not limited to   */
/* any implied warranty of merchantability or fitness for any particular        */
/* purpose, or that the use will not infringe any third party patent, copyright */
/* or trademark. SJTU should not be liable for any loss or damage arising from  */
/* its use. you can redistribute it and/or                                      */
/*  modify it under the terms of the GNU Lesser General Public                  */
/*  License as published by the Free Software Foundation; either                */
/*  version 2 of the License, or (at your option) any later version.            */
/********************************************************************************/
/**
 *        PROJECT: Simple ARM Core
 *      COPYRIGHT: SOME of SJTU 2006
 *       $RCSfile: ,v $
 *      $Revision:  $
 *         AUTHOR: Thomas.Luo
 *         E_MAIL: [e-mail]
 *       LANGUAGE: V
 *    DESCRIPTION: 
 *
 *      DOCUMENTS: 
 **/
`include "sarm9h.v"
module pipectrl(clk,rst,
ifstatus,idstatus,exstatus,mastatus,wbstatus,
ifenable,idenable,exenable,maenable,wbenable,
ifien,idien,exien,maien,wbien
);
input clk;
input rst;
input[1:0] ifstatus;
input[1:0] idstatus;
input[1:0] exstatus;
input[1:0] mastatus;
input[1:0] wbstatus;

wire [1:0] status[0:5];
output ifenable;
output idenable;
output exenable;
output maenable;
output wbenable;

output ifien;
output idien;
output exien;
output maien;
output wbien;
reg control[0:5];

integer i;
reg stall;
assign ifien =1;
assign idien =ifstatus[0];
assign exien =idstatus[0];
assign maien =exstatus[0];
assign wbien =mastatus[0];

assign {ifenable} = control[1];
assign {idenable} = control[2];
assign {exenable} = control[3];
assign {maenable} = control[4];
assign {wbenable} = control[5];
assign status[0] = 'b01;
assign status[1] = ifstatus;
assign status[2] = idstatus;
assign status[3] = exstatus;
assign status[4] = mastatus;
assign status[5] = wbstatus;
always @(posedge clk or negedge rst)
begin
   if (~rst)
	for(i=5;i>=0;i=i-1)
      control[i] <=0;
   else
   begin
       stall =0;
       for(i=5;i>0;i=i-1)
       begin
		   case (status[i])
		   2'b00:
			   begin
				   stall =0;
				   if (status[i-1] == 2'b01)
					   control[i] <=1;
				   else
					   control[i] <=0;
			   end
		   2'b01:
			   begin
				 if (stall)
					 begin
					   control[i]<=0;
					 end
				 else
					 begin
					   control[i]<=1;
					 end
				end
		   2'b10:
			   begin
				   control[i] <=1;
				   stall =1;
			   end
		   default:
			   control[i] <=1;
		 endcase
	  end
     
   end 
end

always @(negedge clk)
begin
 for(i=5;i>0;i=i-1)
	control[i] <=0;
end

endmodule