sarm9.v.bak

别处下载的sarm9

/********************************************************************************/
/* Copyright @ 2006 by SOME of SJTU                                             */
/* All rights are reserved. Reproduction in whole or in part is                 */
/* prohibited without the written consent of the copyright owner.               */
/* SJTU reserves the right to make changes without notice at                    */
/* any time. The software is provided as is and SJTU makes                      */
/* no warranty, expressed, implied or statutory, including but not limited to   */
/* any implied warranty of merchantability or fitness for any particular        */
/* purpose, or that the use will not infringe any third party patent, copyright */
/* or trademark. SJTU should not be liable for any loss or damage arising from  */
/* its use. you can redistribute it and/or                                      */
/*  modify it under the terms of the GNU Lesser General Public                  */
/*  License as published by the Free Software Foundation; either                */
/*  version 2 of the License, or (at your option) any later version.            */
/********************************************************************************/
/**
 *        PROJECT: Simple ARM Core
 *      COPYRIGHT: SOME of SJTU 2006
 *       $RCSfile: ,v $
 *      $Revision:  $
 *         AUTHOR: Thomas.Luo
 *         E_MAIL: [e-mail]
 *       LANGUAGE: V
 *    DESCRIPTION: 
 *
 *      DOCUMENTS: 
 **/
`include "sarm9h.v"
module sarm9(clk,rst,iclk1,iaddr1,idata1,irw1,iclk2,iaddr2,idata2,irw2,dclk,daddr,ddata,drw);
    input clk;
    input rst;
  
    output iclk1;
    output iclk2;
    output dclk;
    output[31:0] iaddr1;
    input [31:0]idata1;
    output irw1;
    output[31:0] iaddr2;
    input [31:0]idata2;
    output irw2;
    
    output [31:0]daddr;
    inout [31:0] ddata;
    output drw;
    integer pcaddr;
    
    ///////////////////////////////////////////////////////////
    //if->id
    wire ifien;
    wire[1:0] ifstatus;   
    wire[31:0] if2idnextpc;
    wire[31:0] if2idnpreg;
    wire[31:0] if2idir;
  
    ///////////////////////////////////////////////////////////
    //id->ex
    wire idien;
    wire[1:0] idstatus;
    wire[7:0]  id2exop;
    wire[3:0]  id2exopt;
    wire[31:0]  id2exrs1;
    wire[31:0] id2exrs2;
    wire[3:0]  id2exrs2op;
    wire[31:0] id2exrs2sf;
    wire[31:0] id2exrdata;
    wire[4:0]  id2exrda;
    wire[3:0]  id2exrsf;
    wire[2:0]  id2exrs1r;
    wire[2:0]  id2exrs2r;
    wire[2:0]  id2exrs2sfr;
    wire[2:0]  id2exrdatar;
    wire id2exsbit;
    wire[31:0] id2pc;
    ///////////////////////////////////////////////////////////
    //ex->ma(ex2ma)
    wire exien;
    wire[1:0] exstatus;
    wire[1:0] ex2maop;
    wire[31:0] ex2maalu;
    wire[4:0] ex2marda;
    
    ///////////////////////////////////////////////////////////
    //ma->wb(ma2wb)
    wire maien;
    wire[1:0] mastatus;
    wire[1:0] ma2wbop;
    wire[31:0] ma2wbdata;
    wire[4:0] ma2wbrda;
    /////////////////////////////////////////////////////////////
    //wb->if
    wire wbien;
    wire[1:0] wbstatus;
    //////////////////////////////////////////////////////////////
    //control
    wire ifenable;
    wire idenable;
    wire exenable;
    wire maenable;
    wire wbenable;
    
    wire ifclk;
    wire idclk;
    wire exclk;
    wire maclk;
    wire wbclk;
    
    
   //============================================================//
    regfile armrf(.rst(rst));
    //============================================================//
    pipeif pif(.clk(ifclk),.rst(rst),.ien(ifien),.status(ifstatus),
    .pc(pcaddr),.iclk(iclk1),.iaddr(iaddr1),.idata(idata1),.irw(irw1),
    .nextpc(if2idnextpc),.npreg(if2idnpreg),
    .ir(if2idir));
   //============================================================// 
    pipeid pid(.clk(idclk),.rst(rst),.ien(idien),.status(idstatus),
    .nextpc(if2idnextpc),.npreg(if2idnpreg),.ir(if2idir),
    .op(id2exop),.opt(id2exopt),.rs1(id2exrs1),
    .rs2(id2exrs2),.rs2op(id2exrs2op),.rs2sf(id2exrs2sf),.rdata(id2exrdata),
    .rda(id2exrda),.rsf(id2exrsf),
    .rs1r(id2exrs1r),.rs2r(id2exrs2r),.rs2sfr(id2exrs2sfr),.rdatar(id2exrdatar),
    .sbit(id2exsbit),
    .npo(id2pc));
    //============================================================//
    pipeex  pex(.clk(exclk),.rst(rst),.ien(exien),.status(exstatus),
    .op(id2exop),.opt(id2exopt),.rs1(id2exrs1),
    .rs2(id2exrs2),.rs2op(id2exrs2op),.rs2sf(id2exrs2sf),.rdata(id2exrdata)
    .rda(id2exrda),.rsf(id2exrsf),
    .rs1r(id2exrs1r),.rs2r(id2exrs2r),.rs2sfr(id2exrs2sfr),.rdatar(id2exrdatar)
    .sbit(id2exsbit),
    .opout(ex2maop),.aluout(ex2maalu),
    .rdaout(ex2marda));
    //============================================================//
    pipema   pma(.clk(maclk),.rst(rst),.ien(maien),.status(mastatus),
    .op(ex2maop),.alu(ex2maalu),.rda(ex2marda),
    .opout(ma2wbop),.data(ma2wbdata),.rdaout(ma2wbrda),
    .iclk(iclk2),.iaddr(iaddr2),.idata(idata2),.irw(irw2),
    .dclk(dclk),.daddr(daddr),.ddata(ddata),.drw(drw));
    //============================================================//
    pipewb   pwb(.clk(wbclk),.rst(rst),.ien(wbien),.status(wbstatus),
    .op(ma2wbop),.data(ma2wbdata),.rda(ma2wbrda));    
        
    //============================================================//
    pipectrl pctrl(.clk(clk),.rst(rst),
    .ifstatus(ifstatus),.idstatus(idstatus),.exstatus(exstatus),
    .mastatus(mastatus),.wbstatus(wbstatus),
    .ifenable(ifenable),.idenable(idenable),
    .exenable(exenable),.maenable(maenable),.wbenable(wbenable),
    .ifien(ifien),.idien(idien),
    .exien(exien),.maien(maien),.wbien(wbien)
    );
    
    
    and ifand(ifclk,ifenable,clk);
    and idand(idclk,idenable,clk);
    and exand(exclk,exenable,clk);
    and maand(maclk,maenable,clk);
    and wband(wbclk,ifenable,clk);
    
    //============================================================//
    always @(negedge ifclk)
    begin
        if ((rst)&&(ifenable))
       pcaddr <= id2pc;
    end
    
    always @(posedge clk or negedge rst)
    begin
        if (~rst)
          pcaddr <=0;
          else
        armrf.regs[15] <= pcaddr;
    end
    
endmodule