pipema.v

别处下载的sarm9

/********************************************************************************/
/* Copyright @ 2006 by SOME of SJTU                                             */
/* All rights are reserved. Reproduction in whole or in part is                 */
/* prohibited without the written consent of the copyright owner.               */
/* SJTU reserves the right to make changes without notice at                    */
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/* no warranty, expressed, implied or statutory, including but not limited to   */
/* any implied warranty of merchantability or fitness for any particular        */
/* purpose, or that the use will not infringe any third party patent, copyright */
/* or trademark. SJTU should not be liable for any loss or damage arising from  */
/* its use. you can redistribute it and/or                                      */
/*  modify it under the terms of the GNU Lesser General Public                  */
/*  License as published by the Free Software Foundation; either                */
/*  version 2 of the License, or (at your option) any later version.            */
/********************************************************************************/
/**
 *        PROJECT: Simple ARM Core
 *      COPYRIGHT: SOME of SJTU 2006
 *       $RCSfile: ,v $
 *      $Revision:  $
 *         AUTHOR: Thomas.Luo
 *         E_MAIL: [e-mail]
 *       LANGUAGE: V
 *    DESCRIPTION: 
 *
 *      DOCUMENTS: 
 **/
`include "sarm9h.v"
module pipema(clk,rst,ien,status,
op,alu,rda,rdata,
opout,data,rdaout,
dclk,daddr,ddata,drw,
iclk,iaddr,idata,irw
);
   input clk;
   input rst;
   input ien;
   output[1:0] status;
   reg[1:0] status;
   
   input[1:0] op;
   input[31:0] alu;
   input[4:0] rda;
   input[31:0] rdata;
   
   /////////////////////////////////////////////
   output[1:0] opout;
   reg [1:0] opout;
   output[31:0] data;
   reg[31:0] data;
   output[4:0] rdaout;
   reg[4:0] rdaout;
   
   reg dclken;
   output dclk;
   output[31:0] daddr;
   reg[31:0] daddr;
   inout[31:0] ddata;
   
   reg[31:0] ddataout;
   output drw;
   reg drw;
   
   
   reg iclken;
   output iclk;
   output[31:0] iaddr;
   reg[31:0] iaddr;
   input[31:0] idata;
   output irw;
   reg irw;
  //////////////////////////////////////////////////////////////////
  
   reg[1:0] iop;
   reg[31:0] ialu;
   reg[4:0] irda;
   reg[31:0] irdata;
   reg iien;
   
   reg[31:0] idataout;
   reg[1:0] iopout;
   reg[1:0] istatus;
  and ick(iclk,iclken,clk); 
  and dck(dclk,dclken,clk); 
  assign ddata = ddataout;
   //////////////////////////////////////////////////////////////////
always @(posedge clk or negedge rst)
begin
   if (~rst)
	   begin
		  status <=0;
		  iclken<=0;
		  iclken<=0;
		  idataout<=0;
		  opout <=0;
		  data<=0;
		  rdaout<=0;
	   end 
   else
       begin
		   if ((status ==2'b00)||(status ==2'b01))
		   begin
				 if (ien)
					  begin
							iop<= op;
							ialu <=alu;
							irda <=rda;
							idataout<= alu;
							iien<= ien;
							status <=2'b01;
							irdata<= rdata;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////							
							
							
							
							
					  end
				  else
					  begin
						  status <=2'b00;
					  end
		   
		   end
	   end
   
end

always @(iop or ialu)
begin
  case(iop)
	   `MAOPNOP:
	   begin
		iopout = `WBOPNOP;
	   end
	   `MAOPLD:
	   begin
		iopout = `WBOPWB;
		ddataout = 32'bzz;
		  if (ialu <'h2000)
		  begin
			 irw = 1;
			 iaddr = ialu;
			 iclken =1;
			 
			 #1
			 idataout = idata;
		  end
		  else
		  begin
			drw =1;
			daddr = ialu -'h2000;
			dclken =1;
			#1
			 idataout = ddata;
		    
		  end
		  

	   end
	   `MAOPST:
	   begin
	   iopout = `WBOPNOP;
		if (ialu <'h2000)
		  begin
		  end
		  else
		  begin
			drw =0;
			daddr = ialu -'h2000;
			ddataout = irdata;
			dclken =1;	    
		  end	   
	   end
	   `MAOPWB:
	   begin
	   iopout = `WBOPWB;
	   end
  endcase
end







always @(negedge clk or negedge rst)
begin
   if (~rst)
	   begin
	   end 
   else
   #5
       begin
		   if ((status ==2'b01))
		   begin
				 if (iien)
					  begin
		
								if (iop == `MAOPLD)
								begin
								//////////////////////////////////////////////////////////
									if (armrf.writealloc[irda])
									 begin
										armrf.data[armrf.reqNaddr[irda]] <= idataout;
										armrf.valid[armrf.reqNaddr[irda]] <=1;
									 end
								/////////////////////////////////////////////////////////
								end				
					  end
		   end
	   end
   
end



always @(negedge clk)
begin
	 dclken <=0;
	 iclken <=0;
	 opout <= iopout;
	 rdaout<=irda;
	 if (iop == `MAOPWB)
		data <= alu;
	 else
		data<= idataout;
end

endmodule