sarmchip.v

别处下载的sarm9

/********************************************************************************/
/* Copyright @ 2006 by SOME of SJTU                                             */
/* All rights are reserved. Reproduction in whole or in part is                 */
/* prohibited without the written consent of the copyright owner.               */
/* SJTU reserves the right to make changes without notice at                    */
/* any time. The software is provided as is and SJTU makes                      */
/* no warranty, expressed, implied or statutory, including but not limited to   */
/* any implied warranty of merchantability or fitness for any particular        */
/* purpose, or that the use will not infringe any third party patent, copyright */
/* or trademark. SJTU should not be liable for any loss or damage arising from  */
/* its use. you can redistribute it and/or                                      */
/*  modify it under the terms of the GNU Lesser General Public                  */
/*  License as published by the Free Software Foundation; either                */
/*  version 2 of the License, or (at your option) any later version.            */
/********************************************************************************/
/**
 *        PROJECT: Simple ARM Core
 *      COPYRIGHT: SOME of SJTU 2006
 *       $RCSfile: ,v $
 *      $Revision:  $
 *         AUTHOR: Thomas.Luo
 *         E_MAIL: [e-mail]
 *       LANGUAGE: V
 *    DESCRIPTION: 
 *
 *      DOCUMENTS: 
 **/
`include "sarm9h.v"
module sarmchip(clk,rst);
    input clk;
    input rst;
    wire iclk1;
    wire[31:0] iaddr1;
    wire[31:0] idata1;
    wire iclk2;
    wire[31:0] iaddr2;
    wire[31:0] idata2;
    wire irw;
    wire dclk;
    wire[31:0] daddr;
    wire[31:0] ddata;
    wire drw;
    
    wire dclk2;
    wire[31:0] daddr2;
    wire[31:0] ddata2;
    wire drw2;
    
   sarm9 arm(.clk(clk),.rst(rst),
   .iclk1(iclk1),.iaddr1(iaddr1),.idata1(idata1),.irw1(irw1),
   .iclk2(iclk2),.iaddr2(iaddr2),.idata2(idata2),.irw2(irw2),
   .dclk(dclk),.daddr(daddr),.ddata(ddata),.drw(drw));
   memory  icache(.clk1(iclk1),.rw1(irw1),.addr1(iaddr1),.data1(idata1),
				  .clk2(iclk2),.rw2(irw2),.addr2(iaddr2),.data2(idata2));
   memory  dcache(.clk1(dclk),.rw1(drw),.addr1(daddr),.data1(ddata),
			.clk2(dclk2),.rw2(drw2),.addr2(daddr2),.data2(ddata2));
endmodule