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📄 memory.v

📁 别处下载的sarm9
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/********************************************************************************//* Copyright @ 2006 by SOME of SJTU                                             *//* All rights are reserved. Reproduction in whole or in part is                 *//* prohibited without the written consent of the copyright owner.               *//* SJTU reserves the right to make changes without notice at                    *//* any time. The software is provided as is and SJTU makes                      *//* no warranty, expressed, implied or statutory, including but not limited to   *//* any implied warranty of merchantability or fitness for any particular        *//* purpose, or that the use will not infringe any third party patent, copyright *//* or trademark. SJTU should not be liable for any loss or damage arising from  *//* its use. you can redistribute it and/or                                      *//*  modify it under the terms of the GNU Lesser General Public                  *//*  License as published by the Free Software Foundation; either                *//*  version 2 of the License, or (at your option) any later version.            *//********************************************************************************//** *        PROJECT: Simple ARM Core *      COPYRIGHT: SOME of SJTU 2006 *       $RCSfile: ,v $ *      $Revision:  $ *         AUTHOR: Thomas.Luo *         E_MAIL: microbear@sjtu.edu.cn *       LANGUAGE: V *    DESCRIPTION:  * *      DOCUMENTS:  **/`include "sarm9h.v"module memory(clk1,rw1,addr1,data1,clk2,rw2,addr2,data2);    input clk1;    input rw1;    input [31:0]addr1;    inout [31:0]data1;        input clk2;    input rw2;    input [31:0]addr2;    inout [31:0]data2;        reg [31:0]  temp2;    reg [31:0]  temp1;    reg [31:0]  mem[0:'h2000];    assign data1 = temp1;    always @(posedge clk1)    begin        if (rw1)           begin              temp1 <= mem[addr1/4];           end        else        begin           temp1 = 'hzzzzzzzz;           mem[addr1/4] <= data1;        end    end        assign data2 = temp2;    always @(posedge clk2)    begin        if (rw2)           begin              temp2 <= mem[addr2/4];           end        else        begin           temp2 = 'hzzzzzzzz;           mem[addr2/4] <= data2;        end    end        endmodule

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