pipewb.v

别处下载的sarm9

/********************************************************************************/
/* Copyright @ 2006 by SOME of SJTU                                             */
/* All rights are reserved. Reproduction in whole or in part is                 */
/* prohibited without the written consent of the copyright owner.               */
/* SJTU reserves the right to make changes without notice at                    */
/* any time. The software is provided as is and SJTU makes                      */
/* no warranty, expressed, implied or statutory, including but not limited to   */
/* any implied warranty of merchantability or fitness for any particular        */
/* purpose, or that the use will not infringe any third party patent, copyright */
/* or trademark. SJTU should not be liable for any loss or damage arising from  */
/* its use. you can redistribute it and/or                                      */
/*  modify it under the terms of the GNU Lesser General Public                  */
/*  License as published by the Free Software Foundation; either                */
/*  version 2 of the License, or (at your option) any later version.            */
/********************************************************************************/
/**
 *        PROJECT: Simple ARM Core
 *      COPYRIGHT: SOME of SJTU 2006
 *       $RCSfile: ,v $
 *      $Revision:  $
 *         AUTHOR: Thomas.Luo
 *         E_MAIL: [e-mail]
 *       LANGUAGE: V
 *    DESCRIPTION: 
 *
 *      DOCUMENTS: 
 **/
`include "sarm9h.v"
module pipewb(clk,rst,ien,status,
op,data,rda
);
   input clk;
   input rst;
   input ien;
   output[1:0] status;
   reg[1:0] status;
   
   input[1:0] op;
   input[31:0] data;
   input[4:0] rda;
   
   integer j;
   integer i;
   
always @(posedge clk or negedge rst)
begin
   if (~rst)
   begin
      status <=0;
   end 
   else
   begin
		if (((status ==2'b00)||(status ==2'b01))&&ien)
			begin
					case (op)
						`WBOPWB:
							 begin						 
								armrf.regs[rda] <= data;
								armrf.writealloc[rda] <=0;
								armrf.reqNaddr[rda] <=4'b1111;
								status <=2'b01;
							 end
							 default:
							  status <=0;
					endcase
			end
	end     
end
always @(posedge clk)
begin
 #2
	for(i=0;i< `MAXRENAMEREGS;i=i+1)
	begin
	  if (armrf.busy[i])
	  begin
			if (armrf.writealloc[armrf.regrename[i]] == 0)
			begin
				   if (!armrf.req[i])
				   begin
  						armrf.busy[i] <= 0;
						armrf.valid[i]<=0;
						armrf.data[i]<=0;
						armrf.regrename[i]<= 0;
				   end
			end
	  end
	end
end

endmodule

/*
always @(posedge clk)
begin
#2
  if (armrf.busy[0])
  begin
		if (armrf.writealloc[armrf.regrename[0]] == 0)
		begin
			   if (!armrf.req[0])
			   begin
  					armrf.busy[0] <= 0;
					armrf.valid[0]<=0;
					armrf.data[0]<=0;
					armrf.regrename[0]<= 0;
			   end
		end
  end
end



always @(posedge clk)
begin
#2
  if (armrf.busy[1])
  begin
		if (armrf.writealloc[armrf.regrename[1]] == 0)
		begin
			   if (!armrf.req[1])
			   begin
  					armrf.busy[1] <= 0;
					armrf.valid[1]<=0;
					armrf.data[1]<=0;
					armrf.regrename[1]<= 0;
			   end
		end
  end
end

always @(posedge clk)
begin
#2
  if (armrf.busy[2])
  begin
		if (armrf.writealloc[armrf.regrename[2]] == 0)
		begin
			   if (!armrf.req[2])
			   begin
  					armrf.busy[2] <= 0;
					armrf.valid[2]<=0;
					armrf.data[2]<=0;
					armrf.regrename[2]<= 0;
			   end
		end
  end
end

always @(posedge clk)
begin
#2
  if (armrf.busy[3])
  begin
		if (armrf.writealloc[armrf.regrename[3]] == 0)
		begin
			   if (!armrf.req[3])
			   begin
  					armrf.busy[3] <= 0;
					armrf.valid[3]<=0;
					armrf.data[3]<=0;
					armrf.regrename[3]<= 0;
			   end
		end
  end
end

always @(posedge clk)
begin
#2
  if (armrf.busy[4])
  begin
		if (armrf.writealloc[armrf.regrename[4]] == 0)
		begin
			   if (!armrf.req[4])
			   begin
  					armrf.busy[4] <= 0;
					armrf.valid[4]<=0;
					armrf.data[4]<=0;
					armrf.regrename[4]<= 0;
			   end
		end
  end
end

always @(posedge clk)
begin
#2
  if (armrf.busy[5])
  begin
		if (armrf.writealloc[armrf.regrename[5]] == 0)
		begin
			   if (!armrf.req[5])
			   begin
  					armrf.busy[5] <= 0;
					armrf.valid[5]<=0;
					armrf.data[5]<=0;
					armrf.regrename[5]<= 0;
			   end
		end
  end
end

always @(posedge clk)
begin
#2
  if (armrf.busy[6])
  begin
		if (armrf.writealloc[armrf.regrename[6]] == 0)
		begin
			   if (!armrf.req[6])
			   begin
  					armrf.busy[6] <= 0;
					armrf.valid[6]<=0;
					armrf.data[6]<=0;
					armrf.regrename[6]<= 0;
			   end
		end
  end
end
*/