pipeid.v

别处下载的sarm9

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/* Copyright @ 2006 by SOME of SJTU                                             */
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/**
 *        PROJECT: Simple ARM Core
 *      COPYRIGHT: SOME of SJTU 2006
 *       $RCSfile: ,v $
 *      $Revision:  $
 *         AUTHOR: Thomas.Luo
 *         E_MAIL: [e-mail]
 *       LANGUAGE: V
 *    DESCRIPTION: 
 *
 *      DOCUMENTS: 
 **/
`include "sarm9h.v"


 
module pipeid(clk,rst,ien,status,
nextpc,npreg,ir,
op,opt,rs1,rs2,rs2op,rs2sf,rda,rdata,
rsf,rs1r,rs2r,rs2sfr,rdatar,sbit,
npo);
/////////////////////////////////////////////////////
   input clk;
   input rst;
   input ien;
   output[1:0] status;
   reg [1:0] status;
   
   reg [1:0] istatus;
////////////////////////////////////////////////////
   input[31:0] nextpc;
   input[31:0] npreg;
   input[31:0] ir;
  ////////////////////////////////////////////////// 
   reg [31:0] inextpc;
   reg [31:0] inpreg;
   reg [31:0] iir;
  ////////////////////////////////////////////////////////// 
   output[7:0] op;//operate code
   reg[7:0] op;
   output[3:0] opt;//operate type
   reg[3:0] opt;
   output[31:0] rs1; // soucre reg1
   reg[31:0] rs1;
   output[31:0] rs2;//soucre reg2
   reg signed[31:0] rs2;
   output[3:0] rs2op;//source reg2 added operate
   reg[3:0] rs2op;
   output[31:0] rs2sf; // source reg2 shift bits
   reg[31:0] rs2sf;
   output[31:0] rdata;// data for store
   reg[31:0] rdata;
   output[4:0] rda; // destination reg address
   reg[4:0] rda;
   output[3:0] rsf;  // rename flags
   reg[3:0] rsf;
   output[`RENAMEREGWIDTH-1:0] rs1r; // source reg1 in rename reg
   reg[`RENAMEREGWIDTH-1:0] rs1r;
   output[`RENAMEREGWIDTH-1:0] rs2r; // source reg2 in rename reg
   reg[`RENAMEREGWIDTH-1:0] rs2r;
   output[`RENAMEREGWIDTH-1:0] rs2sfr;//source reg2 shitf in rename reg
   reg[`RENAMEREGWIDTH-1:0] rs2sfr;
   output[`RENAMEREGWIDTH-1:0] rdatar;// data for store rename
   reg[`RENAMEREGWIDTH-1:0] rdatar;
   output sbit; //S bit, 
   reg sbit;  //Indicates that the instruction updates the condition codes. 
/////////////////////////////////////////////////////
   output[31:0] npo;
   reg[31:0] npo;
   reg[31:0] inpo;
 /////////////////////////////////////////////////////////
   reg[7:0]  iop;
   reg[3:0]  iopt;
   reg[31:0] ir14;
   reg[22:0] off;  // B offset
   integer j;
   integer find;
   reg isjmp;
   function decshift;
   input[1:0] shift;
   case(shift)
   2'b00:
	  decshift = `SFLSL;
   2'b01:
	  decshift = `SFLSR;
   2'b10:
	  decshift = `SFASR;
   2'b11:
	  decshift = `SFROR;
   endcase
   endfunction

 //////////////////////////////////////////////////////////
//EQ ,NE,CS,CC,MI,PL,VS , VC,HI,LS,GE,LT,GT,LE,AL
 
 function testcond;
 input[3:0] cond;
 case(cond)
	 `EQ:
	 begin //z set pass
		 if (armrf.cpsr[30])
		   testcond =1;
		 else
		   testcond =0;
	 end
	 `NE: //z clear
	 begin
		 if (!armrf.cpsr[30])
		   testcond =1;
		 else
		   testcond =0;
	 end
	 `CS: // c set
	 begin
		 if (armrf.cpsr[29])
		   testcond =1;
		 else
		   testcond =0;
	 end
	 `CC: // c clear
	 begin
	 if (!armrf.cpsr[29])
		   testcond =1;
		 else
		   testcond =0;
	 end
	 `MI://  n set
	 begin
		 if (armrf.cpsr[31])
		   testcond =1;
		 else
		   testcond =0;
	 end
	 `PL:  // n clear
	 begin
		 if (!armrf.cpsr[31])
		   testcond =1;
		 else
		   testcond =0;
	 end
	 `VS: //  v set
	 begin
		 if (armrf.cpsr[28])
		   testcond =1;
		 else
		   testcond =0;
	 end
	 `VC: // v clear
	 begin
		 if (!armrf.cpsr[28])
		   testcond =1;
		 else
		   testcond =0;
	 end
	 `HI: // c set and z clear
	 begin
		 if ((armrf.cpsr[29]) &&(!armrf.cpsr[30]))
		   testcond =1;
		 else
		   testcond =0;
	 end
	 `LS: // c clear or z set
	 begin
		 if ((!armrf.cpsr[29])&&(armrf.cpsr[30]))
		   testcond =1;
		 else
		   testcond =0;
	 end 
	 `GE: // n==v
	 begin
		 if (armrf.cpsr[31]==armrf.cpsr[28])
		   testcond =1;
		 else
		   testcond =0;
	 end
	 `LT:  //n!=v
	 begin
		 if (armrf.cpsr[31]!=armrf.cpsr[28])
		   testcond =1;
		 else
		   testcond =0;
	 end
	 `GT:  // z ==0 , N ==V
	 begin
		 if ((!armrf.cpsr[30] )&&
		 (armrf.cpsr[31]==armrf.cpsr[28]))
		   testcond =1;
		 else
		   testcond =0;
	 end
	 `LE: //  z ==1 or n!=v
	 begin
		 if ((armrf.cpsr[30])&&
		 (armrf.cpsr[31]!=armrf.cpsr[28]))
		   testcond =1;
		 else
		   testcond =0;
	 end
	 `AL:  //always 
	 begin
		testcond =1;
	 end
	 default:
	 begin
		testcond =0;
	 end
	endcase
 endfunction
 always @(nextpc or isjmp or nextpc)
 begin
	if (isjmp)
		npo = inpo;
	else
		npo = nextpc;
 end
 always @(posedge clk  or  negedge rst)
 begin
	 if(~rst)
		begin
		npo <= 0;
		inpo<=0;
		isjmp <= 0;  
		status<= 0;
		npo <=0;
		op<=0;
		istatus<=0;
		end
	 else
	 begin
		if ((status ==2'b00)||(status ==2'b01))
		 begin
			if (ien)
			begin
			  isjmp <= 0;  
			  inextpc <=nextpc;
			  inpreg <=npreg;
			  iir <= ir; 
			  rsf <=0;
			  if (armrf.cpsrws)
			   begin
				  istatus<=2'b10; 
			   end
			   istatus <=  2'b01;      
			end
			else
			begin
			  istatus <=  2'b00; 
			end
		 end
		 else // if status
		 begin
				  if (!armrf.cpsrws)
				   begin
					   istatus <=  2'b01;  
					   if (testcond(iir[31:28]))
						  begin		   
						  end
					   else
						  begin
							iir <={iir[31:28],28'b0};    
						  end
				   end
		 end
	  end // end if rst
 end	 
 always @(iir)
 begin
	isjmp =0;
	casex(iir)
		32'b????_0001_0000_????_????_????_????_????://l/s imm
		begin
			iopt = `ENCMRS;
		end
		32'b????_00?1_0010_????_????_????_????_????://l/s reg
		begin
			iopt = `ENCMSR; 
		end
		
		32'b????_010?_????_????_????_????_????_????://l/s imm
		begin
			iopt = `ENCLSIMM;
		end
		32'b????_011?_????_????_????_????_???0_????://l/s reg
		begin
			iopt = `ENCLSREG; 
		end
		32'b????_001?_????_????_????_????_????_????://dp imm
		begin
			iopt = `ENCDPIMM;
		end
		32'b????_000?_????_????_????_????_???0_????://dp imm shift
		begin
			if (iir[15:12] == `R15)
			begin
				iopt = `ENCDPIMMS;
				inpo = armrf.regs[iir[3:0]];
				isjmp =1;
			end
			else
				iopt = `ENCDPIMMS;
		end
		32'b????_000?_????_????_????_????_0??1_????://dp reg shift
		begin
			iopt = `ENCDPREGS;
		end
		32'b????_0000_001?_????_????_????_1001_????://MAL
		begin
			iopt =`ENCMLA;
		end
		32'b????_0000_000?_????_????_????_1001_????://MUL
		begin
			iopt=`ENCMUL;
		end
		32'b????_101?_????_????_????_????_????_????://B or BL
		begin
			op = `NOP;
			iopt = `ENCB;
			if (iir[24])
			begin
				ir14 = inpreg +4;
			end
			if (iir[23])
			   begin
				   off = iir[22:0];
				   off = ~off;
				   off = off+1;
				   off = off<< 2;
				   inpo = nextpc -off ;
				   isjmp =1;
			   end
			   
			else
			   begin
				  off = iir[22:0];
				  off = off<< 2;
				  inpo = nextpc + off;
				  isjmp =1;
			   end
			 
		end
		
		default:
		begin
			iopt =`ENCUNKNOWN;
			istatus =  2'b11;  
		end
	endcase
 end
 
  /*MOV ,ORR,AND ,ADD,ADC,SUB,MVN ,CMP,CMN*/    
 function [7:0] getopcode;
	input [3:0] opi;
	
	case(opi)
		4'b1101:
		getopcode=`MOV;
		4'b1100:
		getopcode=`ORR;
		4'b0000:
		getopcode=`AND;
		4'b0100:
		getopcode=`ADD;
		4'b0101:
		getopcode=`ADC;
		4'b0010:
		getopcode=`SUB;
		4'b1111:
		getopcode=`MVN;
		4'b1010:
		getopcode=`CMP;
		4'b1011:
		getopcode=`CMN;
		default:
		getopcode=`NOP;
   endcase
 endfunction
 /*op;opt;rs1;rs2;rs2op;rs2sf;rda;rsf;rs1r;rs2r;rs2sfr;sbit;*/

always @(negedge clk)
begin
	status<= istatus;
	if (istatus == 2'b01)
	 begin
			 case(iopt)
			 		`ENCMRS:
			 		begin
			 			 op <= `MRS;   
						 opt <= iopt;
						 rs1r<= 0;
						 rsf <= 0;
						 rs1 <= 0;
						 rs2 <= 0;
						 rs2op <= 0;
						 rs2sf <=0;
						 rs2r<=0;
						 rs2sfr<=0;
						 sbit <=0;
						 rdatar<=0;
						 rsf<=0;
						 rdata<= 0;
			 		end
			         `ENCMSR:
			 		begin
			 			 op <= `MSR;   
						 opt <= iopt;
						 
		 				if (iir[25])
		 				 begin
		 					 rsf[0]<= 0;
							 rs1r<= 0; 
							 rs1 <= iir[19:16];
							 rsf[1]<=0;
							 rs2<= iir[7:0];
							 rs2op <=`SFROR;
							 rsf[2]<=0;
							 rs2sf <=iir[11:8];
							 rs2r<=0;
							 rs2sfr<=0;
							 sbit<= 0;				   
							 rdatar<=0;
							 rsf[3]<=0;
							 rdata<= 0;  
		 				 end
		 				 else
		 				 begin
		 					 rsf[0]<= 0;
							 rs1r<= 0; 
							 rs1 <= iir[19:16];
							 
							 if (armrf.writealloc[iir[3:0]])
								begin
								   rs2r <= armrf.reqNaddr[iir[3:0]]; 
								   #1
								   armrf.req[armrf.reqNaddr[iir[3:0]]] <=   armrf.req[armrf.reqNaddr[iir[3:0]]] +1;
																
								   rsf[1] <=1;
								   rs2 <=0;
								end
							 else
								begin
								   rs2r<=0;
								   rsf[1] =0;
								   rs2<= armrf.regs[iir[3:0]];
								end
								
								
							 rs2op <=`SFNOP;
							 rsf[2]<=0;
							 rs2sf <=0;
							 rs2r<=0;
							 rs2sfr<=0;
							 sbit<= 0;				   
							 rdatar<=0;
							 rsf[3]<=0;
							 rdata<= 0;  
		 				 
		 				 
		 				 
			 		     
		 				 end
		 			end
			 
					 `ENCB:
					  begin
					   if (iir[24])
						armrf.regs[14] <=ir14;
						op <=`NOP;
					  end
					 ////////////////////////////////////////////////////////////
					 `ENCLSIMM:
					 begin
					   rda <= iir[15:12];
						 if (iir[20])
							begin
							op <= `LD;
							 rdatar<=0;
						  rsf[3]<=0;
						  rdata<= 0;
							end
						 else
							begin
							  op <= `ST;
							   if (armrf.writealloc[iir[15:12]])
								begin
								   rdatar <= armrf.reqNaddr[iir[15:12]]; 
								   armrf.req[armrf.reqNaddr[iir[15:12]]] <=   armrf.req[armrf.reqNaddr[iir[15:12]]] +1;
																
								   rsf[3]<=1;
								   rdata<=0;
								end
							 else
								begin
								   rdatar<=0;
								   rsf[3]<=0;
								   rdata<= armrf.regs[iir[15:12]];
								end
							end
							
						 opt <= iopt;
						 if (iir[19:16] ==`R15)
						 begin
							rs1r <= 0;
							rsf <= 0;
							rs1 <= npreg;
						 end
						 else
						 begin
							 if (armrf.writealloc[iir[19:16]])
								begin
								   rs1r <= armrf.reqNaddr[iir[19:16]]; 
								   #1
								   armrf.req[armrf.reqNaddr[iir[19:16]]] <=   armrf.req[armrf.reqNaddr[iir[19:16]]] +1;
																
								   rsf[0] <=1;
								   rs1 <=0;
								end
							 else
								begin
								   rs1r<=0;
								   rsf[0] =0;
								   rs1<= armrf.regs[iir[19:16]];
								end